media: ccs-pll: Fix check for PLL multiplier upper bound

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The additional multiplier (for higher VT timing) of the PLL multiplier was
checked against the upper limit but the result was rounded up, possibly
producing too high additional multiplier. Round down instead to keep
within hardware limits.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>

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Sakari Ailus 2020-07-07 15:24:09 +02:00 • committed by Mauro Carvalho Chehab

parent c64cf71d10

commit 82ab97c8c7

1 changed files with 1 additions and 2 deletions

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drivers/media/i2c/ccs-pll.c

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