ARM: tegra: Fix missed EMC registers latching on resume from LP1 on Tegra30+

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The memory interface configuration and re-calibration interval are left
unassigned on resume from LP1 because these registers are shadowed and
require latching after being adjusted.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>

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Dmitry Osipenko 2018-11-25 00:13:46 +03:00 • committed by Thierry Reding

parent bfeffd1552

commit 82cdfc382b

1 changed files with 2 additions and 0 deletions

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arch/arm/mach-tegra/sleep-tegra30.S

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