ARM: 8278/1: sa1100: split irq handling for low GPIOs

Browse source

Low GPIO pins use an interrupt in SC interrupts space. However it's
possible to handle them as if all the GPIO interrupts are instead tied
to single GPIO handler, which later decodes GEDR register and
chain-calls next IRQ handler. So split first 11 interrupts into system
part (IRQ_GPIO0_SC - IRQ_GPIO10_SC) which work exactly like the rest of
system controller interrupts and real GPIO interrupts
(IRQ_GPIO0..IRQ_GPIO10). A single handler sa1100_gpio_handler then
decodes and calls next handler.

Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Tested-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>

...

This commit is contained in:

Dmitry Eremin-Solenikov 2015-01-15 02:29:16 +01:00 • committed by Russell King

parent 7a8ca0a0c4

commit 83508093f4

3 changed files with 93 additions and 69 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

73

arch/arm/mach-sa1100/include/mach/irqs.h

View file

87

arch/arm/mach-sa1100/irq.c

View file

2

drivers/gpio/gpio-sa1100.c

View file