clk: hi3660: fix incorrect uart3 clock freqency

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[ Upstream commit d33fb1b9f0 ]

UART3 clock rate is doubled in previous commit.

This error is not detected until recently a mezzanine board which makes
real use of uart3 port (through LS connector of 96boards) was setup
and tested on hi3660-hikey960 board.

This patch changes clock source rate of clk_factor_uart3 to 100000000.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Sasha Levin <alexander.levin@verizon.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Zhong Kaihua 2017-08-07 22:51:56 +08:00 • committed by Greg Kroah-Hartman

parent a967ab0f73

commit 8356c5754c

1 changed files with 1 additions and 1 deletions

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drivers/clk/hisilicon/clk-hi3660.c

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