iommu/riscv: Include the dword number in RISCV_IOMMU_CMD macros

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The command queue entry format is 128 bits. Follow the pattern of the
other drivers and encode the 64 bit dword number in the macro
itself. RISC-V further has similarly named macros that are not field
layout macros, but field content macros which won't get a new number.

Overall this is clearer to understand the code and check for errors like
using the wrong macro in the wrong spot.

Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Tomasz Jeznach <tjeznach@rivosinc.com>
Tested-by: Andrew Jones <andrew.jones@oss.qualcomm.com>
Signed-off-by: Joerg Roedel <joerg.roedel@amd.com>

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Jason Gunthorpe 2026-05-08 11:53:06 -03:00 • committed by Joerg Roedel

parent e4084c6bbb

commit 835d06ee7e

1 changed files with 51 additions and 51 deletions

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drivers/iommu/riscv/iommu-bits.h

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