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Merge branch 'pci/cxl'

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- Lock the upstream bridge while using it to perform a Secondary Bus Reset
  (Dave Jiang)

- Return failure when attempting Secondary Bus Reset below a CXL Port that
  has SBR masked (Dave Jiang)

- Add a "cxl_bus" reset method that temporarily unmasks SBR (Dave Jiang)

- Add a warning if we reset a CXL type 3 memory device that was in use
  while being reset (Dave Jiang)

* pci/cxl:
  cxl: Add post-reset warning if reset results in loss of previously committed HDM decoders
  PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports
  PCI/CXL: Fail bus reset if upstream CXL Port has SBR masked
  PCI: Lock upstream bridge for pci_reset_function()
  PCI/CXL: Move CXL Vendor ID to pci_ids.h
This commit is contained in:
Bjorn Helgaas 2024-05-16 18:14:09 -05:00
commit 83711a1ab2
13 changed files with 175 additions and 8 deletions
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