clk: exynos5433: Extend list of available AUD_PLL output frequencies

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Add one more entry to the exynos5433_aud_pll_rates table, this allows
to support audio sample rates: 48000, 96000, 192000 Hz with minimum
error. The M, P, S, K values re confirmed by the HW team.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>

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Sylwester Nawrocki 2018-02-12 16:52:27 +01:00

parent 5c7979246e

commit 83942bdd99

1 changed files with 1 additions and 0 deletions

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drivers/clk/samsung/clk-exynos5433.c

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