drm/amd/display: Correct Slice reset calculation

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[Why]
Once DSC slice cannot fit pixel clock, we incorrectly
reset min slices to 0 and allow max slice to operate,
even when max slice itself cannot fit the pixel clock
properly.

[How]
Change the sequence such that we correctly determine
DSC is not possible when both min slices and max
slices cannot fit pixel clock per slice.

Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com>
Acked-by: Alex Hung <alex.hung@amd.com>
Signed-off-by: Chris Park <Chris.Park@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Chris Park 2022-03-15 12:21:43 -04:00 • committed by Alex Deucher

parent e9ebc23b3f

commit 83bb503275

1 changed files with 2 additions and 2 deletions

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drivers/gpu/drm/amd/display/dc/dsc/dc_dsc.c

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