arm64: dts: apple: Add t600x L1/L2 cache properties and nodes

Browse source

The t600x CPU nodes are missing the cache hierarchy information. The
cache hierarchy on Arm can not be detected and needs to be described in
DT. The OS scheduler can make use of this information for scheduling
decisions.

The cache size information is based on various articles about the
processors. There's also an L3 system level cache (SLC). It's not
described here because SLCs typically have some MMIO interface which
would need to be described.

Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Hector Martin <marcan@marcan.st>

...

This commit is contained in:

Rob Herring 2022-11-22 16:06:20 -06:00 • committed by Hector Martin

parent 56fed763f6

commit 83fb5b55cd

2 changed files with 102 additions and 0 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

51

arch/arm64/boot/dts/apple/t6002.dtsi

View file

51

arch/arm64/boot/dts/apple/t600x-common.dtsi

View file