net/mlx5: DR, Fix potential shift wrapping of 32-bit value in STEv1 getter

Browse source

Fix 32-bit variable shift wrapping in dr_ste_v1_get_miss_addr.

Fixes: a6098129c7 ("net/mlx5: DR, Add STEv1 setters and getters")
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com>
Reviewed-by: Alex Vesker <valex@nvidia.com>
Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>

...

This commit is contained in:

Yevgeny Kliteynik 2021-02-06 22:11:52 +02:00 • committed by Saeed Mahameed

parent dc694f11a7

commit 84076c4c80

1 changed files with 2 additions and 2 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

4

drivers/net/ethernet/mellanox/mlx5/core/steering/dr_ste_v1.c

View file