clk: stm32f4: SDIO & 48Mhz clock management for STM32F469 board

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In the stm32f469 soc, the 48Mhz clock could be derived from pll-q or
from pll-sai-p.

The SDIO clock could be also derived from 48Mhz or from sys clock.

Signed-off-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Gabriel Fernandez 2016-12-13 15:20:18 +01:00 • committed by Stephen Boyd

parent 62710c121b

commit 844ca23f5b

1 changed files with 46 additions and 3 deletions

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drivers/clk/clk-stm32f4.c

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