clk: sunxi-ng: gate: Support common pre-dividers

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Some clock gates have a pre-divider between the source input and the
gate itself. A notable example is the HSIC 12 MHz clock found on the
A83T, which has the 24 MHz main oscillator as its input, and a /2
pre-divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

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Chen-Yu Tsai 2017-02-14 11:35:23 +08:00 • committed by Maxime Ripard

parent 9ad0bb39fc

commit 845d6b0ff9

1 changed files with 47 additions and 0 deletions

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drivers/clk/sunxi-ng/ccu_gate.c

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