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Samsung SoC clock drivers changes for v6.20

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1. Add new clock controllers:
    - MFD for ExynosAutov920 SoC,
    - Display Process Unit (DPU) for Google GS101 SoC.
 
 2. Implement automatic clock gating mode (HWACG) for Google GS101 SoC
    clock controllers (but also used on almost all modern Exynos SoC),
    opposed to currently used mode - manual mode.
 
 Background on HW automatic clock gating from Peter Griffin in cover letter:
 
 This series addresses an issue with Samsung Exynos based upstream clock driver
 whereby the upstream clock driver sets all the clock gates into "manual mode"
 (which uses a bit that is documented as reserved in the gate registers).
 
 Another issue with the current "manual clock gating" approach upstream is
 there are many bus/interconnect clocks whose relationships to the IPs
 are not well documented or defined in the specs. When adding a new CMU until
 now we have tried to label these clocks appropriately with CLK_IS_CRITICAL and
 CLK_IGNORE_UNUSED but doing so is both error prone and time consuming. If
 your lucky disabling a critical bus clock causes an immediate hang. Other
 clocks however aren't so obvious and show up through random instability
 some period of time later.
 
 Fortunately each CMU (at least on newer Exynos) provides a "hardware
 automatic clock gating" HWACG feature that is used by the downstream
 Samsung clock drivers. Hardware automatic clock gating uses a hardware
 interface between the CMU and IP to control all clocks required by the
 IP. This interface is called Q-channel, and is part of the Arm AMBA low
 power interface specification [1].
 
 The advantage of using this Qchannel hardware interface for
 enabling/disabling the clocks is that it takes care of all clocks
 (including bus/interconnect) ones for the IP automatically thereby reducing
 the dynamic power.
 
 Whilst each clock component (GATE, MUX, DIV, QCH etc) has a HWACG enable
 bit there are also some "global enable override" bits for the entire CMU in
 the CMU_CONTROLLER_OPTION register.
 
 This series makes use of those "global enable" override bits to enable auto
 clock mode for the entire CMU and every component within it. Through
 experimentation we can see that setting the "manual mode" reserved gate bit
 on a particular gate register overides the global enable bits. So the code
 is updated accordingly not to do that.
 
 Auto clock mode has been implemented as a "opt in" by setting a new
 auto_clock_gate flag in the CMU static data. The intention is existing
 platforms in manual mode should not be effected by any of these changes.
 
 If auto_clock_mode flag is set and the option_offset field is specified
 then the global enable override bits will be written for the
 CMU (to avoid relying on any prior bootstage configuration). Again if auto
 mode is enabled the code no longer sets MANUAL and clears HWACG bits on
 each gate register.
 
 To ensure compatibility with older DTs (that specified an incorrect CMU
 size) the resource size is checked and the driver falls back to manual
 clock gate mode in such cases. As the CLK_IGNORE_UNUSED and CLK_IS_CRITICAL
 flags are required for manual clock gate mode, the patch removing these
 flags has been dropped from v2. I tested with an old DT and we successfully
 switch to manual clock gate mode and the system correctly boots.
 
 To have dynamic root clock gating (drcg) of bus components and memclk
 enabled, it is required to set the bus_component_drcg and memclk registers
 in the correspondingly named sysreg controller. If auto clock mode is
 enabled the clock driver will now attempt to get the sysreg syscon via the
 samsung,sysreg property (as used by other Exynos drivers upstream) and set
 the registers accordingly. The suspend/resume code paths are also updated
 to handle saving/restoring registers using a regmap. Note cmu_top is an
 exception and does not have a corresondingly named sysreg_top.
 
 As all clock gates are currently exposed in the gs101 drivers and DT, we
 continue to register all of these gates in auto clock mode, but with some new
 samsung_auto_clk_gate_ops. As clk enable and clk disable are now handled by
 Q-channel interface the .enable and .disable implementations are
 no-ops. However by using some CMU qchannel debug registers we can report
 the current clock status (enabled or disabled) of every clock gate in the
 system. This has the nice effect of still being able to dump the entire
 clock tree from /sys/kernel/debug/clk/clk_summary and see a live view of
 every auto clock in the system.
 
 With the infrastructure in place, all the CMUs registered in clk-gs101 are
 now updated to enable auto clock mode. From dumping
 /sys/kernel/debug/clk/clk_summary it is possible to see that after enabling
 auto clock mode approximately 305 clocks are enabled, and 299 are now
 disabled. This number goes up and down a bit by 3-5 clocks just on a idle
 system sat at a console.
 
 With auto clock mode enabled it is now also possible to boot without the
 clk_ignore_unused kernel command line property for the first time!
 
 For future CMUs in gs101 I propose we continue to expose all gates, but
 register the CMU in "auto mode". For new device drivers or updates to
 existing dt bindings related to clocks to support gs101 I suggest we only
 use the "obviously correct" clock(s). By "obviously correct" I mean a clock
 has the IP name in the clock register name, but not try to deduce other
 obsucurely named bus/interconnect clocks which will now all be handled
 automatically. Note it is still possible to test whether the "obviously
 correct" clock is indeed correct by putting the individual gate in manual
 mode and disabling the clock (e.g. by using devmem).
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Merge tag 'samsung-clk-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into clk-samsung

Pull Samsung clk driver updates from Krzysztof Kozlowski:

1. Add new clock controllers:
   - MFD for ExynosAutov920 SoC,
   - Display Process Unit (DPU) for Google GS101 SoC.

2. Implement automatic clock gating mode (HWACG) for Google GS101 SoC
   clock controllers (but also used on almost all modern Exynos SoC),
   opposed to currently used mode - manual mode.

Background on HW automatic clock gating from Peter Griffin in cover letter:

This series addresses an issue with Samsung Exynos based upstream clock driver
whereby the upstream clock driver sets all the clock gates into "manual mode"
(which uses a bit that is documented as reserved in the gate registers).

Another issue with the current "manual clock gating" approach upstream is
there are many bus/interconnect clocks whose relationships to the IPs
are not well documented or defined in the specs. When adding a new CMU until
now we have tried to label these clocks appropriately with CLK_IS_CRITICAL and
CLK_IGNORE_UNUSED but doing so is both error prone and time consuming. If
your lucky disabling a critical bus clock causes an immediate hang. Other
clocks however aren't so obvious and show up through random instability
some period of time later.

Fortunately each CMU (at least on newer Exynos) provides a "hardware
automatic clock gating" HWACG feature that is used by the downstream
Samsung clock drivers. Hardware automatic clock gating uses a hardware
interface between the CMU and IP to control all clocks required by the
IP. This interface is called Q-channel, and is part of the Arm AMBA low
power interface specification [1].

The advantage of using this Qchannel hardware interface for
enabling/disabling the clocks is that it takes care of all clocks
(including bus/interconnect) ones for the IP automatically thereby reducing
the dynamic power.

Whilst each clock component (GATE, MUX, DIV, QCH etc) has a HWACG enable
bit there are also some "global enable override" bits for the entire CMU in
the CMU_CONTROLLER_OPTION register.

This series makes use of those "global enable" override bits to enable auto
clock mode for the entire CMU and every component within it. Through
experimentation we can see that setting the "manual mode" reserved gate bit
on a particular gate register overides the global enable bits. So the code
is updated accordingly not to do that.

Auto clock mode has been implemented as a "opt in" by setting a new
auto_clock_gate flag in the CMU static data. The intention is existing
platforms in manual mode should not be effected by any of these changes.

If auto_clock_mode flag is set and the option_offset field is specified
then the global enable override bits will be written for the
CMU (to avoid relying on any prior bootstage configuration). Again if auto
mode is enabled the code no longer sets MANUAL and clears HWACG bits on
each gate register.

To ensure compatibility with older DTs (that specified an incorrect CMU
size) the resource size is checked and the driver falls back to manual
clock gate mode in such cases. As the CLK_IGNORE_UNUSED and CLK_IS_CRITICAL
flags are required for manual clock gate mode, the patch removing these
flags has been dropped from v2. I tested with an old DT and we successfully
switch to manual clock gate mode and the system correctly boots.

To have dynamic root clock gating (drcg) of bus components and memclk
enabled, it is required to set the bus_component_drcg and memclk registers
in the correspondingly named sysreg controller. If auto clock mode is
enabled the clock driver will now attempt to get the sysreg syscon via the
samsung,sysreg property (as used by other Exynos drivers upstream) and set
the registers accordingly. The suspend/resume code paths are also updated
to handle saving/restoring registers using a regmap. Note cmu_top is an
exception and does not have a corresondingly named sysreg_top.

As all clock gates are currently exposed in the gs101 drivers and DT, we
continue to register all of these gates in auto clock mode, but with some new
samsung_auto_clk_gate_ops. As clk enable and clk disable are now handled by
Q-channel interface the .enable and .disable implementations are
no-ops. However by using some CMU qchannel debug registers we can report
the current clock status (enabled or disabled) of every clock gate in the
system. This has the nice effect of still being able to dump the entire
clock tree from /sys/kernel/debug/clk/clk_summary and see a live view of
every auto clock in the system.

With the infrastructure in place, all the CMUs registered in clk-gs101 are
now updated to enable auto clock mode. From dumping
/sys/kernel/debug/clk/clk_summary it is possible to see that after enabling
auto clock mode approximately 305 clocks are enabled, and 299 are now
disabled. This number goes up and down a bit by 3-5 clocks just on a idle
system sat at a console.

With auto clock mode enabled it is now also possible to boot without the
clk_ignore_unused kernel command line property for the first time!

For future CMUs in gs101 I propose we continue to expose all gates, but
register the CMU in "auto mode". For new device drivers or updates to
existing dt bindings related to clocks to support gs101 I suggest we only
use the "obviously correct" clock(s). By "obviously correct" I mean a clock
has the IP name in the clock register name, but not try to deduce other
obsucurely named bus/interconnect clocks which will now all be handled
automatically. Note it is still possible to test whether the "obviously
correct" clock is indeed correct by putting the individual gate in manual
mode and disabling the clock (e.g. by using devmem).

* tag 'samsung-clk-6.20' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  clk: samsung: gs101: add support for Display Process Unit (DPU) clocks
  dt-bindings: samsung: exynos-sysreg: add gs101 dpu compatible
  dt-bindings: clock: google,gs101-clock: Add DPU clock management unit
  dt-bindings: clock: google,gs101-clock: fix alphanumeric ordering
  clk: samsung: fix sysreg save/restore when PM is enabled for CMU
  clk: samsung: avoid warning message on legacy Exynos (auto clock gating)
  clk: samsung: gs101: Enable auto_clock_gate mode for each gs101 CMU
  clk: samsung: Implement automatic clock gating mode for CMUs
  dt-bindings: clock: google,gs101-clock: add samsung,sysreg property as required
  clk: samsung: exynosautov920: add clock support
  dt-bindings: clock: exynosautov920: add MFD clock definitions
This commit is contained in:
Stephen Boyd 2026-01-22 18:09:44 -08:00
commit 847eaf0d31
16 changed files with 812 additions and 50 deletions
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