clk: iproc: Fix error in the pll post divider rate calculation

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The pll post divider code was using DIV_ROUND_UP when determining the
divider value best suited to produce the target frequency.
Using DIV_ROUND_CLOSEST will give us better divider values when
the division results in a small remainder.
Also, change the post divider clock over to the determine_rate api
instead of round_rate.

Signed-off-by: Simran Rai <ssimran@broadcom.com>
Signed-off-by: Lori Hikichi <lori.hikichi@broadcom.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>

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Lori Hikichi 2017-08-14 12:00:39 -07:00 • committed by Stephen Boyd

parent becf123772

commit 85151a6b0b

1 changed files with 17 additions and 16 deletions

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drivers/clk/bcm/clk-iproc-pll.c

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