From 853d77cc0c06e686d0214a015fe88c1047ba6302 Mon Sep 17 00:00:00 2001 From: Dan Carpenter Date: Tue, 21 Jul 2026 09:12:41 -0700 Subject: [PATCH] arm64: dts: s32g: Add GPR syscon region Add the GPR syscon region for the s32 chipset. Signed-off-by: Dan Carpenter [jkangas@redhat.com: GPR syscon resized from 0x3000 to 0x100] Signed-off-by: Jared Kangas Signed-off-by: Frank Li --- arch/arm64/boot/dts/freescale/s32g2.dtsi | 6 ++++++ arch/arm64/boot/dts/freescale/s32g3.dtsi | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/arch/arm64/boot/dts/freescale/s32g2.dtsi b/arch/arm64/boot/dts/freescale/s32g2.dtsi index 8dc0c5d9f368..996494e34593 100644 --- a/arch/arm64/boot/dts/freescale/s32g2.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g2.dtsi @@ -122,6 +122,11 @@ clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g2-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -814,6 +819,7 @@ compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq"; diff --git a/arch/arm64/boot/dts/freescale/s32g3.dtsi b/arch/arm64/boot/dts/freescale/s32g3.dtsi index 24fa3057e929..31f7aad00b76 100644 --- a/arch/arm64/boot/dts/freescale/s32g3.dtsi +++ b/arch/arm64/boot/dts/freescale/s32g3.dtsi @@ -180,6 +180,11 @@ clock-names = "ipg", "source0"; }; + gpr: syscon@4007c000 { + compatible = "nxp,s32g3-gpr", "syscon"; + reg = <0x4007c000 0x100>; + }; + pinctrl: pinctrl@4009c240 { compatible = "nxp,s32g2-siul2-pinctrl"; /* MSCR0-MSCR101 registers on siul2_0 */ @@ -893,6 +898,7 @@ compatible = "nxp,s32g2-dwmac"; reg = <0x4033c000 0x2000>, /* gmac IP */ <0x4007c004 0x4>; /* GMAC_0_CTRL_STS */ + nxp,phy-sel = <&gpr 0x4>; interrupt-parent = <&gic>; interrupts = ; interrupt-names = "macirq";