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Support for Rockchip's PX30 SoC including its new half-divider
clock type that is doing freq_out = 2*freq_in / (2*div + 3). As well as a register-bit fix for the rk3399 i2sout clock. -----BEGIN PGP SIGNATURE----- iQFEBAABCAAuFiEE7v+35S2Q1vLNA3Lx86Z5yZzRHYEFAltGCcYQHGhlaWtvQHNu dGVjaC5kZQAKCRDzpnnJnNEdgR5BB/9wg6TYAEkrFKeOCHbpvYMYF019+TBUETg9 ZTu7LNT64oKcLNvrZnAgD3y/NVXVCrq5ef0PdP3dWDspymGjB/yiJMQwIYEaWnbN pqcceqmVbyfb+bK5IfSFxNhufTNr/yLxkH7HV47YcPIkojcLBUMzHQcu+Yy4OlI9 h53U+DdpfEk5V2AAQDz6vOkW6WgBXdJna68oTGlvbem9FEQGOZ1tIygWUBUUwAGO +rEhProWMut9U7sd95/CwPGv0tSIkQNKFwCybaai8UZCfHpCSB4hu9CEVx4YVvxA h5DQtc2fiE8B+tx+tfCPZ/d/Rp+tN23pnHbz9lhySZb8AoXpeVOI =Xsdh -----END PGP SIGNATURE----- Merge tag 'v4.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-rockchip Pull Rockchip clk driver updates from Heiko Stuebner: Support for Rockchip's PX30 SoC including its new half-divider clock type that is doing freq_out = 2*freq_in / (2*div + 3). As well as a register-bit fix for the rk3399 i2sout clock. * tag 'v4.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: clk: rockchip: fix clk_i2sout parent selection bits on rk3399 clk: rockchip: add clock controller for px30 clk: rockchip: add support for half divider dt-bindings: add bindings for px30 clock controller clk: rockchip: add dt-binding header for px30
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