KVM: MMU: Add 5 level EPT & Shadow page table support.

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Extends the shadow paging code, so that 5 level shadow page
table can be constructed if VM is running in 5 level paging
mode.

Also extends the ept code, so that 5 level ept table can be
constructed if maxphysaddr of VM exceeds 48 bits. Unlike the
shadow logic, KVM should still use 4 level ept table for a VM
whose physical address width is less than 48 bits, even when
the VM is running in 5 level paging mode.

Signed-off-by: Yu Zhang <yu.c.zhang@linux.intel.com>
[Unconditionally reset the MMU context in kvm_cpuid_update.
 Changing MAXPHYADDR invalidates the reserved bit bitmasks.
 - Paolo]
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

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This commit is contained in:

Yu Zhang 2017-08-24 20:27:55 +08:00 • committed by Paolo Bonzini

parent 2a7266a8f9

commit 855feb6736

9 changed files with 67 additions and 29 deletions

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10

arch/x86/include/asm/kvm_host.h

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2

arch/x86/include/asm/vmx.h

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1

arch/x86/kvm/cpuid.c

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43

arch/x86/kvm/mmu.c

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1

arch/x86/kvm/mmu.h

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4

arch/x86/kvm/mmu_audit.c

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4

arch/x86/kvm/svm.c

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arch/x86/kvm/vmx.c

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10

arch/x86/kvm/x86.h

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