arm: tcc8k: Choose PLL settings conforming to board layout

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The evaluation board is driven with 1.2V core voltage, so system clock
must not exceed 192 MHz, bus clock must not exceed 110 MHz. Choose
appropriate values and set DTCMWAIT accordingly. Adapt UART setting to
avoid console log interruption and wait for the specified locking time
of 300us to pass.

Signed-off-by: Oskar Schirmer <oskar@linutronix.de>
Cc: bigeasy@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>

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Oskar Schirmer 2011-02-17 16:42:58 +01:00 • committed by Thomas Gleixner

parent 30d913556b

commit 85922e54a3

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arch/arm/mach-tcc8k/board-tcc8000-sdk.c

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