clk: exynos5433: Fix wrong PMS value of exynos5433_pll_rates

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This patch fixes the wrong PMS value of exynos5433_pll_rates table
for {ATLAS|APOLLO|MEM0|MEM1|BUS|MFC|MPHY|G3D|DISP|ISP|_PLL.
- 720 MHz (mdiv=360, pdiv=6, sdiv=1) -> 700 MHz (mdiv=175, pdiv=3, sdiv=1)
- 350 MHz (mdiv=360, pdiv=6, sdiv=2) -> (mdiv=350, pdiv=6, sdiv=2)
- 133 MHz (mdiv=552, pdiv=6, sdiv=4) -> (mdiv=532, pdiv=6, sdiv=4)

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

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Chanwoo Choi 2015-04-27 20:36:32 +09:00 • committed by Sylwester Nawrocki

parent b57c93be79

commit 85943d7ea5

1 changed files with 3 additions and 3 deletions

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drivers/clk/samsung/clk-exynos5433.c

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