drm/i915/tgl: Fix Media power gate sequence.

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Some media power gates are disabled by default. commit 5d86923060
("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
tried to enable it, but it duplicated an existent register.
So, the main PG setup sequences ended up overwriting it.

So, let's now merge this to the main PG setup sequence.

v2: (Chris): s/BIT/REG_BIT, remove useless comment,
    	     remove useless =0, use the right gt,
	     remove rc6 sequence doubt from commit message.

Fixes: 5d86923060 ("drm/i915/tgl: Enable VD HCP/MFX sub-pipe power gating")
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: stable@vger.kernel.org#v5.5+
Cc: Dale B Stimson <dale.b.stimson@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20201111072859.1186070-1-rodrigo.vivi@intel.com
(cherry picked from commit 695dc55b57)
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

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This commit is contained in:

Rodrigo Vivi 2020-11-11 09:09:36 -05:00

parent 5ce6861d36

commit 85a12d7eb8

3 changed files with 22 additions and 25 deletions

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22

drivers/gpu/drm/i915/gt/intel_rc6.c

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12

drivers/gpu/drm/i915/i915_reg.h

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13

drivers/gpu/drm/i915/intel_pm.c

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