diff --git a/drivers/gpu/drm/amd/ras/core/aca.c b/drivers/gpu/drm/amd/ras/core/aca.c index 898742e57834..8bb93ca61b18 100644 --- a/drivers/gpu/drm/amd/ras/core/aca.c +++ b/drivers/gpu/drm/amd/ras/core/aca.c @@ -619,6 +619,10 @@ int ras_aca_sw_init(struct ras_core_context *ras_core) memset(ras_aca, 0, sizeof(*ras_aca)); + ras_aca->aca_blk = kcalloc(RAS_BLOCK_ID__LAST, sizeof(struct aca_block), GFP_KERNEL); + if (!ras_aca->aca_blk) + return -ENOMEM; + for (blk = 0; blk < RAS_BLOCK_ID__LAST; blk++) { aca_blk = &ras_aca->aca_blk[blk]; aca_blk->ecc.socket_num_per_node = socket_num_per_node; @@ -642,6 +646,7 @@ int ras_aca_sw_fini(struct ras_core_context *ras_core) { struct ras_aca *ras_aca = &ras_core->ras_aca; + kfree(ras_aca->aca_blk); mutex_destroy(&ras_aca->aca_lock); mutex_destroy(&ras_aca->bank_op_lock); diff --git a/drivers/gpu/drm/amd/ras/core/aca.h b/drivers/gpu/drm/amd/ras/core/aca.h index d81a9d0ccc6d..a9538e64d7d5 100644 --- a/drivers/gpu/drm/amd/ras/core/aca.h +++ b/drivers/gpu/drm/amd/ras/core/aca.h @@ -29,7 +29,6 @@ #define MAX_SOCKET_NUM_PER_NODE 8 #define MAX_AID_NUM_PER_SOCKET 4 #define MAX_XCD_NUM_PER_AID 4 -#define MAX_ACA_RAS_BLOCK 20 #define ACA_ERROR__UE_MASK (0x1 << RAS_ERR_TYPE__UE) #define ACA_ERROR__CE_MASK (0x1 << RAS_ERR_TYPE__CE) @@ -153,7 +152,7 @@ struct ras_aca { const struct ras_aca_ip_func *ip_func; struct mutex aca_lock; struct mutex bank_op_lock; - struct aca_block aca_blk[MAX_ACA_RAS_BLOCK]; + struct aca_block *aca_blk; uint32_t ue_updated_mark; }; diff --git a/drivers/gpu/drm/amd/ras/core/cmd.c b/drivers/gpu/drm/amd/ras/core/cmd.c index 98767a94d267..a0e61826c292 100644 --- a/drivers/gpu/drm/amd/ras/core/cmd.c +++ b/drivers/gpu/drm/amd/ras/core/cmd.c @@ -357,48 +357,6 @@ static int ras_cmd_get_batch_trace_records(struct ras_core_context *ras_core, return RAS_CMD__SUCCESS; } -static enum ras_ta_block __get_ras_ta_block(enum ras_block_id block) -{ - switch (block) { - case RAS_BLOCK_ID__UMC: - return RAS_TA_BLOCK__UMC; - case RAS_BLOCK_ID__SDMA: - return RAS_TA_BLOCK__SDMA; - case RAS_BLOCK_ID__GFX: - return RAS_TA_BLOCK__GFX; - case RAS_BLOCK_ID__MMHUB: - return RAS_TA_BLOCK__MMHUB; - case RAS_BLOCK_ID__ATHUB: - return RAS_TA_BLOCK__ATHUB; - case RAS_BLOCK_ID__PCIE_BIF: - return RAS_TA_BLOCK__PCIE_BIF; - case RAS_BLOCK_ID__HDP: - return RAS_TA_BLOCK__HDP; - case RAS_BLOCK_ID__XGMI_WAFL: - return RAS_TA_BLOCK__XGMI_WAFL; - case RAS_BLOCK_ID__DF: - return RAS_TA_BLOCK__DF; - case RAS_BLOCK_ID__SMN: - return RAS_TA_BLOCK__SMN; - case RAS_BLOCK_ID__SEM: - return RAS_TA_BLOCK__SEM; - case RAS_BLOCK_ID__MP0: - return RAS_TA_BLOCK__MP0; - case RAS_BLOCK_ID__MP1: - return RAS_TA_BLOCK__MP1; - case RAS_BLOCK_ID__FUSE: - return RAS_TA_BLOCK__FUSE; - case RAS_BLOCK_ID__MCA: - return RAS_TA_BLOCK__MCA; - case RAS_BLOCK_ID__VCN: - return RAS_TA_BLOCK__VCN; - case RAS_BLOCK_ID__JPEG: - return RAS_TA_BLOCK__JPEG; - default: - return RAS_TA_BLOCK__UMC; - } -} - static enum ras_ta_error_type __get_ras_ta_err_type(enum ras_ecc_err_type error) { switch (error) { @@ -426,7 +384,6 @@ static int ras_cmd_inject_error(struct ras_core_context *ras_core, (struct ras_cmd_inject_error_rsp *)cmd->output_buff_raw; int ret = 0; struct ras_ta_trigger_error_input block_info = { - .block_id = __get_ras_ta_block(req->block_id), .sub_block_index = req->subblock_id, .inject_error_type = __get_ras_ta_err_type(req->error_type), .address = req->address, @@ -437,6 +394,12 @@ static int ras_cmd_inject_error(struct ras_core_context *ras_core, (cmd->output_buf_size < sizeof(*output_data))) return RAS_CMD__ERROR_INVALID_INPUT_SIZE; + ret = ras_psp_get_block_ta_id(ras_core, req->block_id, &block_info.block_id); + if (ret == -RAS_CORE_NOT_SUPPORTED) + return RAS_CMD__ERROR_UNSUPPORT; + else if (ret) + return ret; + ret = ras_psp_trigger_error(ras_core, &block_info, req->instance_mask); if (!ret) { output_data->version = 0; diff --git a/drivers/gpu/drm/amd/ras/core/cmd.h b/drivers/gpu/drm/amd/ras/core/cmd.h index e3b39866455d..4950d0561b30 100644 --- a/drivers/gpu/drm/amd/ras/core/cmd.h +++ b/drivers/gpu/drm/amd/ras/core/cmd.h @@ -92,6 +92,7 @@ enum ras_cmd_response { RAS_CMD__ERROR_ACCESS_DENIED, RAS_CMD__ERROR_GENERIC, RAS_CMD__ERROR_TIMEOUT, + RAS_CMD__ERROR_UNSUPPORT, }; enum ras_error_type { diff --git a/drivers/gpu/drm/amd/ras/core/ras.h b/drivers/gpu/drm/amd/ras/core/ras.h index 74c9d8652144..39a272344ee2 100644 --- a/drivers/gpu/drm/amd/ras/core/ras.h +++ b/drivers/gpu/drm/amd/ras/core/ras.h @@ -82,6 +82,26 @@ enum ras_block_id { RAS_BLOCK_ID__JPEG, RAS_BLOCK_ID__IH, RAS_BLOCK_ID__MPIO, + RAS_BLOCK_ID__MMSCH, + RAS_BLOCK_ID__MP5, + RAS_BLOCK_ID__ATU, + RAS_BLOCK_ID__DACC_BE, + RAS_BLOCK_ID__ECLR, + RAS_BLOCK_ID__KPX_SERDES, + RAS_BLOCK_ID__LSDMA, + RAS_BLOCK_ID__MPART, + RAS_BLOCK_ID__MPIFOE, + RAS_BLOCK_ID__MPRAS, + RAS_BLOCK_ID__NBIF, + RAS_BLOCK_ID__NBIO, + RAS_BLOCK_ID__OXRP, + RAS_BLOCK_ID__PCIE_PL, + RAS_BLOCK_ID__PCS_XGMI, + RAS_BLOCK_ID__PIE, + RAS_BLOCK_ID__CS, + RAS_BLOCK_ID__SHUB, + RAS_BLOCK_ID__SSBDCI, + RAS_BLOCK_ID__UCIE_PCS, RAS_BLOCK_ID__LAST }; diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp.c b/drivers/gpu/drm/amd/ras/core/ras_psp.c index 0f4ced7ddfbe..5628b384a733 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_psp.c +++ b/drivers/gpu/drm/amd/ras/core/ras_psp.c @@ -716,6 +716,10 @@ int ras_psp_hw_init(struct ras_core_context *ras_core) if (!psp->ip_func) return -EINVAL; + if (psp->ip_func->get_ras_block_maps && + psp->ip_func->get_ras_block_maps(ras_core, + &psp->blk_maps, &psp->maps_size)) + return -EINVAL; /* After GPU reset, the system RAS PSP status may change. * therefore, it is necessary to synchronize the system status again. */ @@ -756,3 +760,26 @@ bool ras_psp_check_supported_cmd(struct ras_core_context *ras_core, return ret; } + +int ras_psp_get_block_ta_id(struct ras_core_context *ras_core, + uint32_t ras_id, uint32_t *ta_id) +{ + struct ras_psp *psp = &ras_core->ras_psp; + int i; + + if (!ta_id || !psp->blk_maps || !psp->maps_size) { + RAS_DEV_ERR(ras_core->dev, "Invalid ras block parameter\n"); + return -EINVAL; + } + + for (i = 0; i < psp->maps_size; i++) { + if (psp->blk_maps[i].ras_id == ras_id) { + *ta_id = psp->blk_maps[i].ta_id; + return 0; + } + } + + RAS_DEV_WARN(ras_core->dev, "Ras block %u is not supported\n", ras_id); + + return -RAS_CORE_NOT_SUPPORTED; +} diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp.h b/drivers/gpu/drm/amd/ras/core/ras_psp.h index c899d0ac74cc..5265408ddafe 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_psp.h +++ b/drivers/gpu/drm/amd/ras/core/ras_psp.h @@ -64,9 +64,15 @@ struct gpu_mem_block { void *private; }; +struct ras_block_map { + uint32_t ras_id; + uint32_t ta_id; +}; struct ras_psp_ip_func { uint32_t (*psp_ras_ring_wptr_get)(struct ras_core_context *ras_core); int (*psp_ras_ring_wptr_set)(struct ras_core_context *ras_core, uint32_t wptr); + int (*get_ras_block_maps)(struct ras_core_context *ras_core, + struct ras_block_map **blk_maps, uint32_t *maps_size); }; struct ras_psp_ring { @@ -108,6 +114,8 @@ struct ras_ta_ctx { struct ras_psp { uint32_t psp_ip_version; + struct ras_block_map *blk_maps; + uint32_t maps_size; struct ras_psp_ring psp_ring; struct ras_psp_ctx psp_ctx; struct ras_ta_ctx ta_ctx; @@ -143,4 +151,6 @@ int ras_psp_query_address(struct ras_core_context *ras_core, struct ras_ta_query_address_output *addr_out); bool ras_psp_check_supported_cmd(struct ras_core_context *ras_core, enum ras_ta_cmd_id cmd_id); +int ras_psp_get_block_ta_id(struct ras_core_context *ras_core, + uint32_t ras_id, uint32_t *ta_id); #endif diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c index 626cf39b75ac..92e617eca879 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_psp_v13_0.c @@ -27,6 +27,28 @@ #define regMP0_SMN_C2PMSG_67 0x0083 #define regMP0_SMN_C2PMSG_67_BASE_IDX 0 +static struct ras_block_map ras_block_maps_v13_0[] = { + {RAS_BLOCK_ID__UMC, RAS_TA_BLOCK__UMC}, + {RAS_BLOCK_ID__SDMA, RAS_TA_BLOCK__SDMA}, + {RAS_BLOCK_ID__GFX, RAS_TA_BLOCK__GFX}, + {RAS_BLOCK_ID__MMHUB, RAS_TA_BLOCK__MMHUB}, + {RAS_BLOCK_ID__ATHUB, RAS_TA_BLOCK__ATHUB}, + {RAS_BLOCK_ID__PCIE_BIF, RAS_TA_BLOCK__PCIE_BIF}, + {RAS_BLOCK_ID__HDP, RAS_TA_BLOCK__HDP}, + {RAS_BLOCK_ID__XGMI_WAFL, RAS_TA_BLOCK__XGMI_WAFL}, + {RAS_BLOCK_ID__DF, RAS_TA_BLOCK__DF}, + {RAS_BLOCK_ID__SMN, RAS_TA_BLOCK__SMN}, + {RAS_BLOCK_ID__SEM, RAS_TA_BLOCK__SEM}, + {RAS_BLOCK_ID__MP0, RAS_TA_BLOCK__MP0}, + {RAS_BLOCK_ID__MP1, RAS_TA_BLOCK__MP1}, + {RAS_BLOCK_ID__FUSE, RAS_TA_BLOCK__FUSE}, + {RAS_BLOCK_ID__MCA, RAS_TA_BLOCK__MCA}, + {RAS_BLOCK_ID__VCN, RAS_TA_BLOCK__VCN}, + {RAS_BLOCK_ID__JPEG, RAS_TA_BLOCK__JPEG}, + {RAS_BLOCK_ID__IH, RAS_TA_BLOCK__IH}, + {RAS_BLOCK_ID__MPIO, RAS_TA_BLOCK__MPIO}, + {RAS_BLOCK_ID__MMSCH, RAS_TA_BLOCK__MMSCH}, +}; static uint32_t ras_psp_v13_0_ring_wptr_get(struct ras_core_context *ras_core) { @@ -40,7 +62,19 @@ static int ras_psp_v13_0_ring_wptr_set(struct ras_core_context *ras_core, uint32 return 0; } +static int ras_psp_v13_0_get_ras_block_maps(struct ras_core_context *ras_core, + struct ras_block_map **blk_maps, uint32_t *maps_size) +{ + if (!blk_maps || !maps_size) + return -EINVAL; + + *blk_maps = ras_block_maps_v13_0; + *maps_size = ARRAY_SIZE(ras_block_maps_v13_0); + + return 0; +} const struct ras_psp_ip_func ras_psp_v13_0 = { .psp_ras_ring_wptr_get = ras_psp_v13_0_ring_wptr_get, .psp_ras_ring_wptr_set = ras_psp_v13_0_ring_wptr_set, + .get_ras_block_maps = ras_psp_v13_0_get_ras_block_maps, }; diff --git a/drivers/gpu/drm/amd/ras/core/ras_psp_v15_0.c b/drivers/gpu/drm/amd/ras/core/ras_psp_v15_0.c index 4f4b323c7032..74f00eec4078 100644 --- a/drivers/gpu/drm/amd/ras/core/ras_psp_v15_0.c +++ b/drivers/gpu/drm/amd/ras/core/ras_psp_v15_0.c @@ -23,11 +23,45 @@ */ #include "ras.h" +#include "ta_if.h" #include "ras_psp_v15_0.h" #define regMPASP_SMN_C2PMSG_67 0x0083 #define regMPASP_SMN_C2PMSG_67_BASE_IDX 1 +static struct ras_block_map ras_block_maps_v15_0[] = { + {RAS_BLOCK_ID__UMC, RAS_TA_MPASP_BLOCK__UMC}, + {RAS_BLOCK_ID__SDMA, RAS_TA_MPASP_BLOCK__SDMA}, + {RAS_BLOCK_ID__GFX, RAS_TA_MPASP_BLOCK__GFX}, + {RAS_BLOCK_ID__MMHUB, RAS_TA_MPASP_BLOCK__MMHUB}, + {RAS_BLOCK_ID__ATHUB, RAS_TA_MPASP_BLOCK__ATHUB}, + {RAS_BLOCK_ID__PCIE_BIF, RAS_TA_MPASP_BLOCK__PCIE}, + {RAS_BLOCK_ID__SMN, RAS_TA_MPASP_BLOCK__SMN}, + {RAS_BLOCK_ID__MP0, RAS_TA_MPASP_BLOCK__MP0}, + {RAS_BLOCK_ID__MP1, RAS_TA_MPASP_BLOCK__MP1}, + {RAS_BLOCK_ID__VCN, RAS_TA_MPASP_BLOCK__VCN}, + {RAS_BLOCK_ID__IH, RAS_TA_MPASP_BLOCK__IH}, + {RAS_BLOCK_ID__MP5, RAS_TA_MPASP_BLOCK__MP5}, + {RAS_BLOCK_ID__ATU, RAS_TA_MPASP_BLOCK__ATU}, + {RAS_BLOCK_ID__DACC_BE, RAS_TA_MPASP_BLOCK__DACC_BE}, + {RAS_BLOCK_ID__ECLR, RAS_TA_MPASP_BLOCK__ECLR}, + {RAS_BLOCK_ID__KPX_SERDES, RAS_TA_MPASP_BLOCK__KPX_SERDES}, + {RAS_BLOCK_ID__LSDMA, RAS_TA_MPASP_BLOCK__LSDMA}, + {RAS_BLOCK_ID__MPART, RAS_TA_MPASP_BLOCK__MPART}, + {RAS_BLOCK_ID__MPIFOE, RAS_TA_MPASP_BLOCK__MPIFOE}, + {RAS_BLOCK_ID__MPRAS, RAS_TA_MPASP_BLOCK__MPRAS}, + {RAS_BLOCK_ID__NBIF, RAS_TA_MPASP_BLOCK__NBIF}, + {RAS_BLOCK_ID__NBIO, RAS_TA_MPASP_BLOCK__NBIO}, + {RAS_BLOCK_ID__OXRP, RAS_TA_MPASP_BLOCK__OXRP}, + {RAS_BLOCK_ID__PCIE_PL, RAS_TA_MPASP_BLOCK__PCIE_PL}, + {RAS_BLOCK_ID__PCS_XGMI, RAS_TA_MPASP_BLOCK__PCS_XGMI}, + {RAS_BLOCK_ID__PIE, RAS_TA_MPASP_BLOCK__PIE}, + {RAS_BLOCK_ID__CS, RAS_TA_MPASP_BLOCK__CS}, + {RAS_BLOCK_ID__SHUB, RAS_TA_MPASP_BLOCK__SHUB}, + {RAS_BLOCK_ID__SSBDCI, RAS_TA_MPASP_BLOCK__SSBDCI}, + {RAS_BLOCK_ID__UCIE_PCS, RAS_TA_MPASP_BLOCK__UCIE_PCS}, +}; + static uint32_t ras_psp_v15_0_ring_wptr_get(struct ras_core_context *ras_core) { return RAS_DEV_RREG32_SOC15(ras_core->dev, MP0, 0, regMPASP_SMN_C2PMSG_67); @@ -40,7 +74,19 @@ static int ras_psp_v15_0_ring_wptr_set(struct ras_core_context *ras_core, uint32 return 0; } +static int ras_psp_v15_0_get_ras_block_maps(struct ras_core_context *ras_core, + struct ras_block_map **blk_maps, uint32_t *maps_size) +{ + if (!blk_maps || !maps_size) + return -EINVAL; + + *blk_maps = ras_block_maps_v15_0; + *maps_size = ARRAY_SIZE(ras_block_maps_v15_0); + + return 0; +} const struct ras_psp_ip_func ras_psp_v15_0 = { .psp_ras_ring_wptr_get = ras_psp_v15_0_ring_wptr_get, .psp_ras_ring_wptr_set = ras_psp_v15_0_ring_wptr_set, + .get_ras_block_maps = ras_psp_v15_0_get_ras_block_maps, }; diff --git a/drivers/gpu/drm/amd/ras/core/ta_if.h b/drivers/gpu/drm/amd/ras/core/ta_if.h index 6b05c82679c0..5d4cea459954 100644 --- a/drivers/gpu/drm/amd/ras/core/ta_if.h +++ b/drivers/gpu/drm/amd/ras/core/ta_if.h @@ -101,6 +101,40 @@ enum ras_ta_block { RAS_TA_NUM_BLOCK_MAX }; +enum ras_ta_mpasp_block { + RAS_TA_MPASP_BLOCK__UMC = 0, + RAS_TA_MPASP_BLOCK__GFX, + RAS_TA_MPASP_BLOCK__SDMA, + RAS_TA_MPASP_BLOCK__MMHUB, + RAS_TA_MPASP_BLOCK__ATHUB, + RAS_TA_MPASP_BLOCK__PCIE, + RAS_TA_MPASP_BLOCK__SMN, + RAS_TA_MPASP_BLOCK__MP0, + RAS_TA_MPASP_BLOCK__MP1, + RAS_TA_MPASP_BLOCK__VCN, + RAS_TA_MPASP_BLOCK__IH, + RAS_TA_MPASP_BLOCK__MP5, + RAS_TA_MPASP_BLOCK__ATU, + RAS_TA_MPASP_BLOCK__DACC_BE, + RAS_TA_MPASP_BLOCK__ECLR, + RAS_TA_MPASP_BLOCK__KPX_SERDES, + RAS_TA_MPASP_BLOCK__LSDMA, + RAS_TA_MPASP_BLOCK__MPART, + RAS_TA_MPASP_BLOCK__MPIFOE, + RAS_TA_MPASP_BLOCK__MPRAS, + RAS_TA_MPASP_BLOCK__NBIF, + RAS_TA_MPASP_BLOCK__NBIO, + RAS_TA_MPASP_BLOCK__OXRP, + RAS_TA_MPASP_BLOCK__PCIE_PL, + RAS_TA_MPASP_BLOCK__PCS_XGMI, + RAS_TA_MPASP_BLOCK__PIE, + RAS_TA_MPASP_BLOCK__CS, + RAS_TA_MPASP_BLOCK__SHUB, + RAS_TA_MPASP_BLOCK__SSBDCI, + RAS_TA_MPASP_BLOCK__UCIE_PCS, + RAS_TA_MPASP_NUM_BLOCK_MAX +}; + enum ras_ta_mca_block { RAS_TA_MCA_BLOCK__MP0 = 0, RAS_TA_MCA_BLOCK__MP1 = 1,