drm/amd/display: fix workaround for incorrect double buffer register for DLG ADL and TTU

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[Why]
these registers should have been double buffered. SW workaround we will have SW program the more aggressive (lower) values
whenever we are upating this register, so we will not have underflow at expense of less optimzal request pattern.

[How]
there is a driver bug where we don't check for 0, which is uninitialzed HW default.  since 0 is smaller than any value we need to program,
driver end up with not programming these registers

Signed-off-by: Tony Cheng <tony.cheng@amd.com>
Reviewed-by: Yongqiang Sun <yongqiang.sun@amd.com>
Acked-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Tony Cheng 2020-01-28 16:00:22 +08:00 • committed by Alex Deucher

parent 96577cf82a

commit 85e148fb96

1 changed files with 25 additions and 10 deletions

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drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c

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