perf/x86/intel/uncore: Add Sapphire Rapids server IMC support

Browse source

The Sapphire Rapids IMC provides the interface to the DRAM and
communicates to the rest of the uncore through the M2M block.

The layout of the control registers for a IMC uncore unit is a little
bit different from the generic one. There is a fixed counter for IMC.
So a specific format and ops are required. Expose the common MMIO ops
which can be reused.

Signed-off-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Andi Kleen <ak@linux.intel.com>
Link: https://lore.kernel.org/r/1625087320-194204-8-git-send-email-kan.liang@linux.intel.com

...

This commit is contained in:

Kan Liang 2021-06-30 14:08:31 -07:00 • committed by Peter Zijlstra

parent 0654dfdc7e

commit 85f2e30f98

3 changed files with 45 additions and 6 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

10

arch/x86/events/intel/uncore_discovery.c

View file

6

arch/x86/events/intel/uncore_discovery.h

View file

35

arch/x86/events/intel/uncore_snbep.c

View file