drm/amdgpu: Add RLC_PG_DELAY_3 for Vangogh

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Driver should enable the CGPG feature for RLC in safe mode to
prevent any misalignment or conflict in middle of any power
feature entry/exit sequence.
Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1,
and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG
hysteresis value in refclk count.

Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Jinzhou Su <Jinzhou.Su@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

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Jinzhou Su 2021-01-19 17:33:36 +08:00 • committed by Alex Deucher

parent d96dd7ef3f

commit 860cc26a01

1 changed files with 15 additions and 0 deletions

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drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

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