clk: axi-clkgen: Add support for fractional dividers

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The axi-clkgen has (optional) fractional dividers on the output clock
divider and feedback clock divider path. Utilizing the fractional dividers
allows for a better resolution of the output clock, being able to
synthesize more frequencies.

Rework the driver support to support the fractional register fields, both
for setting a new rate as well as reading back the current rate from the
hardware.

For setting the rate if no perfect divider settings were found in
non-fractional mode try again in fractional mode and see if better settings
can be found. This appears to be the recommended mode of operation.

Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Alexandru Ardelean <alexandru.ardelean@analog.com>
Link: https://lore.kernel.org/r/20201001085948.21412-1-alexandru.ardelean@analog.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Lars-Peter Clausen 2020-10-01 11:59:47 +03:00 • committed by Stephen Boyd

parent 9123e3a74e

commit 86378cf646

1 changed files with 129 additions and 51 deletions

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drivers/clk/clk-axi-clkgen.c

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