clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider

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The clock was missing CLK_SET_RATE_PARENT flag, which caused rate
setting failures due to inability of reconfiguration of second
divider behind it.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

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Tomasz Figa 2013-12-21 07:58:38 +09:00 • committed by Kukjin Kim

parent a98e3190fc

commit 86576fbe20

1 changed files with 2 additions and 1 deletions

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drivers/clk/samsung/clk-exynos4.c

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