drm/i915: Improve WRPLL reference clock readout on HSW/BDW

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On non-ULT HSW the "special" WRPLL reference clock select
actually means non-SSC. Take that into account when reading
out the WRPLL state.

Also the non-SSC reference may be either 24MHz or 135MHz,
which we can read out from FUSE_STRAP3. The BDW docs actually
say: "also indicates whether the CPU and PCH are in a single
package or separate packages", so it may be that this is not
actually required and we could just assume 135 MHz (just like
the code already did). But it doesn't really hurt to read this
out as the HSW docs aren't quite so clear.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190604200933.29417-5-ville.syrjala@linux.intel.com
Reviewed-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

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This commit is contained in:

Ville Syrjälä 2019-06-04 23:09:33 +03:00

parent d1707a96b1

commit 86761789b3

2 changed files with 17 additions and 1 deletions

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3

drivers/gpu/drm/i915/i915_reg.h

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15

drivers/gpu/drm/i915/intel_ddi.c

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