MIPS: DTS: CI20: Parent MSCMUX clock to MPLL

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This makes it possible to clock the SD cards much higher, as the MPLL is
running at 1.2 GHz by default. The previous parent was the EXT clock,
which caused the SD cards to be clocked at 24 MHz maximum.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>

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Paul Cercueil 2023-06-04 16:56:39 +02:00 • committed by Thomas Bogendoerfer

parent 5fe60d3b68

commit 868b70b9e6

1 changed files with 3 additions and 2 deletions

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arch/mips/boot/dts/ingenic/ci20.dts

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