PCI: cadence: Add post-link delay for LGA and j721e glue driver

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The Cadence LGA (Legacy Architecture IP) PCIe host controller currently
lacks the mandatory 100 ms delay after link training completes for speeds
> 5.0 GT/s, as required by PCIe r6.0 sec 6.6.1.

Add a 'max_link_speed' field to struct cdns_pcie. In the common host
layer function cdns_pcie_host_start_link(), after the link has been
successfully established, call pci_host_common_link_train_delay() to
insert the required delay.

For the j721e glue driver, set cdns_pcie.max_link_speed from the existing
link speed logic. For other LGA-based glue drivers (sky1, sg2042), the
common LGA host setup (pcie-cadence-host.c) provides a fallback reading
of the device tree property "max-link-speed" when available. This ensures
that the delay is not missed on those platforms once they enable the
property.

Signed-off-by: Hans Zhang <18255117159@163.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260518004246.1384532-3-18255117159@163.com

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Hans Zhang 2026-05-18 08:42:41 +08:00 • committed by Manivannan Sadhasivam

parent 29fbf582e7

commit 869317b95f

4 changed files with 11 additions and 0 deletions

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1

drivers/pci/controller/cadence/pci-j721e.c

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4

drivers/pci/controller/cadence/pcie-cadence-host-common.c

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4

drivers/pci/controller/cadence/pcie-cadence-host.c

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2

drivers/pci/controller/cadence/pcie-cadence.h

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