drm/i915/cnl: WaDisableI2mCycleOnWRPort

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On CNL B0 stepping GAM is not able to detect some deadlock
condition and then rise the rise the gam_coh_flush.

WA database and spec both mentions to set 4AB8[24]=1 as
workaround. Although register offset 0x4AB8 is not
documented for any platform.

References: HSD#1945815, BSID#1112

Cc: Mika Kuoppala <mika.kuoppala@intel.com>
Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170829230751.21047-1-rodrigo.vivi@intel.com

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Rodrigo Vivi 2017-08-29 16:07:51 -07:00

parent 392572feb0

commit 86ebb015fa

2 changed files with 6 additions and 0 deletions

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1

drivers/gpu/drm/i915/i915_reg.h

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5

drivers/gpu/drm/i915/intel_engine_cs.c

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