From b0a07f609600b6fa4c30f783db50c38456804485 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jul 2020 18:51:40 +0200 Subject: [PATCH 01/20] ARM: dts: stm32: Move ethernet PHY into DH SoM DT The PHY and the VIO regulator is populated on the SoM, move it into the SoM DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 33 ----------------- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 36 +++++++++++++++++++ 2 files changed, 36 insertions(+), 33 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 7c4bd615b311..9cf6d90fbf69 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -11,7 +11,6 @@ aliases { serial0 = &uart4; serial1 = &usart3; serial2 = &uart8; - ethernet0 = ðernet0; }; chosen { @@ -33,16 +32,6 @@ display_bl: display-bl { status = "okay"; }; - ethernet_vio: vioregulator { - compatible = "regulator-fixed"; - regulator-name = "vio"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; - regulator-always-on; - regulator-boot-on; - }; - gpio-keys-polled { compatible = "gpio-keys-polled"; #size-cells = <0>; @@ -141,28 +130,6 @@ &cec { status = "okay"; }; -ðernet0 { - status = "okay"; - pinctrl-0 = <ðernet0_rmii_pins_a>; - pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; - pinctrl-names = "default", "sleep"; - phy-mode = "rmii"; - max-speed = <100>; - phy-handle = <&phy0>; - st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; - - mdio0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "snps,dwmac-mdio"; - - phy0: ethernet-phy@1 { - reg = <1>; - }; - }; -}; - &i2c2 { /* Header X22 */ pinctrl-names = "default"; pinctrl-0 = <&i2c2_pins_a>; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index ba905196fb54..d30a3c60da9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -9,6 +9,10 @@ #include / { + aliases { + ethernet0 = ðernet0; + }; + memory@c0000000 { device_type = "memory"; reg = <0xC0000000 0x40000000>; @@ -55,6 +59,16 @@ retram: retram@38000000 { no-map; }; }; + + ethernet_vio: vioregulator { + compatible = "regulator-fixed"; + regulator-name = "vio"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + gpio = <&gpiog 3 GPIO_ACTIVE_LOW>; + regulator-always-on; + regulator-boot-on; + }; }; &adc { @@ -94,6 +108,28 @@ &dts { status = "okay"; }; +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rmii_pins_a>; + pinctrl-1 = <ðernet0_rmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rmii"; + max-speed = <100>; + phy-handle = <&phy0>; + st,eth-ref-clk-sel; + phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + + phy0: ethernet-phy@1 { + reg = <1>; + }; + }; +}; + &i2c4 { pinctrl-names = "default"; pinctrl-0 = <&i2c4_pins_a>; From fde180f06d7bc71c457879615cfc070a66a76ce0 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 29 Jul 2020 18:51:41 +0200 Subject: [PATCH 02/20] ARM: dts: stm32: Add DHSOM based DRC02 board Add DT for DH DRC02 unit, which is a universal controller device. The system has two ethernet ports, two CANs, RS485 and RS232, USB, capacitive buttons and an OLED display. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 1 + arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts | 35 ++++ arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts | 4 +- .../arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi | 157 ++++++++++++++++++ 4 files changed, 195 insertions(+), 2 deletions(-) create mode 100644 arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts create mode 100644 arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 4572db3fa5ae..8cdcf7316ca2 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1047,6 +1047,7 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32746g-eval.dtb \ stm32h743i-eval.dtb \ stm32h743i-disco.dtb \ + stm32mp153c-dhcom-drc02.dtb \ stm32mp157a-avenger96.dtb \ stm32mp157a-dhcor-avenger96.dtb \ stm32mp157a-dk1.dtb \ diff --git a/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts new file mode 100644 index 000000000000..02a39132958e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp153c-dhcom-drc02.dts @@ -0,0 +1,35 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + * + * DHCOM STM32MP1 variant: + * DHCM-STM32MP153C-C065-R102-F0819-SPI-E2-CAN2-RTC-I-01D2 + * DHCOM PCB number: 587-200 or newer + * DRC02 PCB number: 568-100 or newer + */ +/dts-v1/; + +#include "stm32mp153.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15xx-dhcom-som.dtsi" +#include "stm32mp15xx-dhcom-drc02.dtsi" + +/ { + model = "DH electronics STM32MP153C DHCOM DRC02"; + compatible = "dh,stm32mp153c-dhcom-drc02", "dh,stm32mp153c-dhcom-som", + "st,stm32mp153"; +}; + +&m_can1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can1_pins_a>; + pinctrl-1 = <&m_can1_sleep_pins_a>; + status = "okay"; +}; + +&m_can2 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&m_can2_pins_a>; + pinctrl-1 = <&m_can2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts index 197aa98d49e2..d3b81382f97c 100644 --- a/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts +++ b/arch/arm/boot/dts/stm32mp157c-dhcom-pdk2.dts @@ -4,7 +4,7 @@ * * DHCOM STM32MP1 variant: * DHCM-STM32MP157C-C065-R102-F0819-SPI-E2-CAN2-SDR104-RTC-WBT-T-DSI-I-01D2 - * DHCOR PCB number: 587-200 or newer + * DHCOM PCB number: 587-200 or newer * PDK2 PCB number: 516-400 or newer */ /dts-v1/; @@ -15,7 +15,7 @@ #include "stm32mp15xx-dhcom-pdk2.dtsi" / { - model = "DH Electronics STM32MP157C DHCOM Premium Developer Kit (2)"; + model = "DH electronics STM32MP157C DHCOM Premium Developer Kit (2)"; compatible = "dh,stm32mp157c-dhcom-pdk2", "dh,stm32mp157c-dhcom-som", "st,stm32mp157"; }; diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi new file mode 100644 index 000000000000..62ab23824a3e --- /dev/null +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-drc02.dtsi @@ -0,0 +1,157 @@ +// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause +/* + * Copyright (C) 2020 Marek Vasut + */ + +#include +#include + +/ { + aliases { + serial0 = &uart4; + serial1 = &usart3; + serial2 = &uart8; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +&adc { + status = "disabled"; +}; + +&dac { + status = "disabled"; +}; + +&gpiob { + /* + * NOTE: On DRC02, the RS485_RX_En is controlled by a separate + * GPIO line, however the STM32 UART driver assumes RX happens + * during TX anyway and that it only controls drive enable DE + * line. Hence, the RX is always enabled here. + */ + rs485-rx-en { + gpio-hog; + gpios = <8 GPIO_ACTIVE_HIGH>; + output-low; + line-name = "rs485-rx-en"; + }; +}; + +&gpiod { + gpio-line-names = "", "", "", "", + "", "", "", "", + "", "", "", "Out1", + "Out2", "", "", ""; +}; + +&gpioi { + gpio-line-names = "In1", "", "", "", + "", "", "", "", + "In2", "", "", "", + "", "", "", ""; + + /* + * NOTE: The USB Hub on the DRC02 needs a reset signal to be + * pulled high in order to be detected by the USB Controller. + * This signal should be handled by USB power sequencing in + * order to reset the Hub when USB bus is powered down, but + * so far there is no such functionality. + */ + usb-hub { + gpio-hog; + gpios = <2 GPIO_ACTIVE_HIGH>; + output-high; + line-name = "usb-hub-reset"; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + status = "okay"; + + eeprom@50 { + compatible = "atmel,24c04"; + reg = <0x50>; + pagesize = <16>; + }; +}; + +&i2c5 { /* TP7/TP8 */ + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc3 { + /* + * On DRC02, the SoM does not have SDIO WiFi. The pins + * are used for on-board microSD slot instead. + */ + /delete-property/broken-cd; + cd-gpios = <&gpioi 10 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; +}; + +&spi1 { + pinctrl-names = "default"; + pinctrl-0 = <&spi1_pins_a>; + cs-gpios = <&gpioz 3 0>; + /* Use PIO for the display */ + /delete-property/dmas; + /delete-property/dma-names; + status = "disabled"; /* Enable once there is display driver */ + /* + * Note: PF3/GPIO_A , PD6/GPIO_B , PG0/GPIO_C , PC6/GPIO_E are + * also connected to the display board connector. + */ +}; + +&usart3 { + pinctrl-names = "default"; + pinctrl-0 = <&usart3_pins_a>; + status = "okay"; +}; + +/* + * Note: PI3 is UART1_RTS and PI5 is UART1_CTS on DRC02 (uart4 of STM32MP1), + * however the STM32MP1 pinmux cannot map them to UART4 . + */ + +&uart8 { /* RS485 */ + linux,rs485-enabled-at-boot-time; + pinctrl-names = "default"; + pinctrl-0 = <&uart8_pins_a>; + rts-gpios = <&gpioe 6 GPIO_ACTIVE_HIGH>; + status = "okay"; +}; + +&usbh_ehci { + phys = <&usbphyc_port0>; + status = "okay"; +}; + +&usbphyc { + status = "okay"; +}; + +&usbphyc_port0 { + phy-supply = <&vdd_usb>; + vdda1v1-supply = <®11>; + vdda1v8-supply = <®18>; +}; From 1ad6e36ec266cedb0d274aa13253ff1fb2eed4ba Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 31 Jul 2020 01:27:57 +0200 Subject: [PATCH 03/20] ARM: dts: stm32: Fix sdmmc2 pins on AV96 The AV96 uses sdmmc2_d47_pins_c and sdmmc2_d47_sleep_pins_c, which differ from sdmmc2_d47_pins_b and sdmmc2_d47_sleep_pins_b in one pin, SDMMC2_D5, which is PA15 in the former and PA9 in the later. The PA15 is correct on AV96, so fix this. This error is likely a result of rebasing across the stm32mp1 DT pinctrl rework. Fixes: 611325f68102 ("ARM: dts: stm32: Add eMMC attached to SDMMC2 on AV96") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 930202742a3f..905cd7bb98cf 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -295,9 +295,9 @@ &sdmmc1 { &sdmmc2 { pinctrl-names = "default", "opendrain", "sleep"; - pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_b>; - pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; - pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_c>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_c>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_c>; bus-width = <8>; mmc-ddr-1_8v; no-sd; From 4e0ec51f8b9ec3802330a431357e955f552a3f99 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Mon, 3 Aug 2020 12:22:54 +0200 Subject: [PATCH 04/20] ARM: dts: stm32: Add USB OTG support to DH PDK2 The DH PDK2 board is capable of USB OTG on the X14 USB Mini-AB connector, fill in the missing bits to make USB OTG possible instead of peripheral. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 9cf6d90fbf69..9e93f0a0d293 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -281,9 +281,12 @@ &usbh_ehci { }; &usbotg_hs { - dr_mode = "peripheral"; - phys = <&usbphyc_port1 0>; + dr_mode = "otg"; + pinctrl-0 = <&usbotg_hs_pins_a>; + pinctrl-names = "default"; phy-names = "usb2-phy"; + phys = <&usbphyc_port1 0>; + vbus-supply = <&vbus_otg>; status = "okay"; }; From 42a31ac6698681363363d48335559d212a26a7ca Mon Sep 17 00:00:00 2001 From: Holger Assmann Date: Fri, 7 Aug 2020 17:03:56 +0200 Subject: [PATCH 05/20] ARM: dts: stm32: lxa-mc1: Fix kernel warning about PHY delays The KSZ9031 PHY skew timings for rxc/txc, originally set to achieve the desired phase shift between clock- and data-signal, now trigger a kernel warning when used in rgmii-id mode: *-skew-ps values should be used only with phy-mode = "rgmii" This is because commit bcf3440c6dd7 ("net: phy: micrel: add phy-mode support for the KSZ9031 PHY") now configures own timings when phy-mode = "rgmii-id". Device trees wanting to set their own delays should use phy-mode "rgmii" instead as the warning prescribes. The "standard" timings now used with "rgmii-id" work fine on this board, so drop the explicit timings in the device tree and thereby silence the warning. Fixes: 666b5ca85cd3 ("ARM: dts: stm32: add STM32MP1-based Linux Automation MC-1 board") Signed-off-by: Holger Assmann Acked-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 2 -- 1 file changed, 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index 5700e6b700d3..b85025d00943 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -121,8 +121,6 @@ ethphy: ethernet-phy@3 { /* KSZ9031RN */ reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ interrupt-parent = <&gpioa>; interrupts = <6 IRQ_TYPE_EDGE_FALLING>; /* ETH_MDINT# */ - rxc-skew-ps = <1860>; - txc-skew-ps = <1860>; reset-assert-us = <10000>; reset-deassert-us = <300>; micrel,force-master; From f3a622297b045e03d07a2e1a6661134505fa8a8d Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:48 +0200 Subject: [PATCH 06/20] dt-bindings: vendor-prefixes: add Seeed Studio Add the "seeed" vendor prefix for Seeed Technology Co., Ltd Website: https://www.seeedstudio.com/ Signed-off-by: Marcin Sloniewski Acked-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Documentation/devicetree/bindings/vendor-prefixes.yaml index 2baee2c817c1..70cfac65dc55 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -910,6 +910,8 @@ patternProperties: description: Schindler "^seagate,.*": description: Seagate Technology PLC + "^seeed,.*": + description: Seeed Technology Co., Ltd "^seirobotics,.*": description: Shenzhen SEI Robotics Co., Ltd "^semtech,.*": From 0e2807579a344dff804b4e111c8ccddb0e2e1feb Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:49 +0200 Subject: [PATCH 07/20] dt-bindings: arm: stm32: document Odyssey compatible Document device tree bindings of Seeed SoM and carrier board. Signed-off-by: Marcin Sloniewski Reviewed-by: Rob Herring Signed-off-by: Alexandre Torgue --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml index 790e6dd48e34..3b318fe15194 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -50,4 +50,10 @@ properties: - const: st,stm32mp157c-ev1 - const: st,stm32mp157c-ed1 - const: st,stm32mp157 + - description: Odyssey STM32MP1 SoM based Boards + items: + - enum: + - seeed,stm32mp157c-odyssey + - const: seeed,stm32mp157c-odyssey-som + - const: st,stm32mp157 ... From be78ab4f632c9f24a58b5bb91c5fb9286ae978c3 Mon Sep 17 00:00:00 2001 From: Marcin Sloniewski Date: Sun, 9 Aug 2020 18:44:50 +0200 Subject: [PATCH 08/20] ARM: dts: stm32: add initial support for stm32mp157-odyssey board Add support for Seeed Studio's stm32mp157c odyssey board. Board consists of SoM with stm32mp157c with 4GB eMMC and 512 MB DDR3 RAM and carrier board with USB and ETH interfaces, SD card connector, wifi and BT chip AP6236. In this patch only basic kernel boot is supported and interfacing SD card and on-board eMMC. Signed-off-by: Marcin Sloniewski Reviewed-by: Ahmad Fatoum Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/Makefile | 3 +- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 18 ++ .../arm/boot/dts/stm32mp157c-odyssey-som.dtsi | 276 ++++++++++++++++++ arch/arm/boot/dts/stm32mp157c-odyssey.dts | 80 +++++ 4 files changed, 376 insertions(+), 1 deletion(-) create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi create mode 100644 arch/arm/boot/dts/stm32mp157c-odyssey.dts diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile index 8cdcf7316ca2..d7653839deb9 100644 --- a/arch/arm/boot/dts/Makefile +++ b/arch/arm/boot/dts/Makefile @@ -1057,7 +1057,8 @@ dtb-$(CONFIG_ARCH_STM32) += \ stm32mp157c-dk2.dtb \ stm32mp157c-ed1.dtb \ stm32mp157c-ev1.dtb \ - stm32mp157c-lxa-mc1.dtb + stm32mp157c-lxa-mc1.dtb \ + stm32mp157c-odyssey.dtb dtb-$(CONFIG_MACH_SUN4I) += \ sun4i-a10-a1000.dtb \ sun4i-a10-ba10-tvbox.dtb \ diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index b5a66429670c..a47eaecbde42 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1437,6 +1437,24 @@ pins { }; }; + sdmmc2_d47_pins_d: sdmmc2-d47-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + + sdmmc2_d47_sleep_pins_d: sdmmc2-d47-sleep-3 { + pins { + pinmux = , /* SDMMC2_D4 */ + , /* SDMMC2_D5 */ + , /* SDMMC2_D6 */ + ; /* SDMMC2_D7 */ + }; + }; + sdmmc3_b4_pins_a: sdmmc3-b4-0 { pins1 { pinmux = , /* SDMMC3_D0 */ diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi new file mode 100644 index 000000000000..6cf49a0a9e69 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey-som.dtsi @@ -0,0 +1,276 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xc.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include +#include +#include + +/ { + model = "Seeed Studio Odyssey-STM32MP157C SOM"; + compatible = "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + memory@c0000000 { + device_type = "memory"; + reg = <0xc0000000 0x20000000>; + }; + + reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + mcuram2: mcuram2@10000000 { + compatible = "shared-dma-pool"; + reg = <0x10000000 0x40000>; + no-map; + }; + + vdev0vring0: vdev0vring0@10040000 { + compatible = "shared-dma-pool"; + reg = <0x10040000 0x1000>; + no-map; + }; + + vdev0vring1: vdev0vring1@10041000 { + compatible = "shared-dma-pool"; + reg = <0x10041000 0x1000>; + no-map; + }; + + vdev0buffer: vdev0buffer@10042000 { + compatible = "shared-dma-pool"; + reg = <0x10042000 0x4000>; + no-map; + }; + + mcuram: mcuram@30000000 { + compatible = "shared-dma-pool"; + reg = <0x30000000 0x40000>; + no-map; + }; + + retram: retram@38000000 { + compatible = "shared-dma-pool"; + reg = <0x38000000 0x10000>; + no-map; + }; + + gpu_reserved: gpu@d4000000 { + reg = <0xd4000000 0x4000000>; + no-map; + }; + }; + + led { + compatible = "gpio-leds"; + led-blue { + color = ; + function = LED_FUNCTION_HEARTBEAT; + gpios = <&gpiog 3 GPIO_ACTIVE_HIGH>; + linux,default-trigger = "heartbeat"; + }; + }; +}; + +&gpu { + contiguous-area = <&gpu_reserved>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins_a>; + i2c-scl-rising-time-ns = <185>; + i2c-scl-falling-time-ns = <20>; + status = "okay"; + /* spare dmas for other usage */ + /delete-property/dmas; + /delete-property/dma-names; + + pmic: stpmic@33 { + compatible = "st,stpmic1"; + reg = <0x33>; + interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; + interrupt-controller; + #interrupt-cells = <2>; + + regulators { + compatible = "st,stpmic1-regulators"; + ldo1-supply = <&v3v3>; + ldo3-supply = <&vdd_ddr>; + ldo6-supply = <&v3v3>; + pwr_sw1-supply = <&bst_out>; + pwr_sw2-supply = <&bst_out>; + + vddcore: buck1 { + regulator-name = "vddcore"; + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd_ddr: buck2 { + regulator-name = "vdd_ddr"; + regulator-min-microvolt = <1350000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + vdd: buck3 { + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + st,mask-reset; + regulator-initial-mode = <0>; + regulator-over-current-protection; + }; + + v3v3: buck4 { + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + regulator-over-current-protection; + regulator-initial-mode = <0>; + }; + + v1v8_audio: ldo1 { + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + interrupts = ; + }; + + v3v3_hdmi: ldo2 { + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + interrupts = ; + }; + + vtt_ddr: ldo3 { + regulator-name = "vtt_ddr"; + regulator-min-microvolt = <500000>; + regulator-max-microvolt = <750000>; + regulator-always-on; + regulator-over-current-protection; + }; + + vdd_usb: ldo4 { + regulator-name = "vdd_usb"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + interrupts = ; + }; + + vdda: ldo5 { + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + interrupts = ; + regulator-boot-on; + }; + + v1v2_hdmi: ldo6 { + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + interrupts = ; + }; + + vref_ddr: vref_ddr { + regulator-name = "vref_ddr"; + regulator-always-on; + regulator-over-current-protection; + }; + + bst_out: boost { + regulator-name = "bst_out"; + interrupts = ; + }; + + vbus_otg: pwr_sw1 { + regulator-name = "vbus_otg"; + interrupts = ; + }; + + vbus_sw: pwr_sw2 { + regulator-name = "vbus_sw"; + interrupts = ; + regulator-active-discharge; + }; + }; + + onkey { + compatible = "st,stpmic1-onkey"; + interrupts = , ; + interrupt-names = "onkey-falling", "onkey-rising"; + power-off-time-sec = <10>; + }; + + watchdog { + compatible = "st,stpmic1-wdt"; + status = "disabled"; + }; + }; +}; + +&ipcc { + status = "okay"; +}; + +&iwdg2 { + timeout-sec = <32>; + status = "okay"; +}; + +&m4_rproc { + memory-region = <&retram>, <&mcuram>, <&mcuram2>, <&vdev0vring0>, + <&vdev0vring1>, <&vdev0buffer>; + mboxes = <&ipcc 0>, <&ipcc 1>, <&ipcc 2>; + mbox-names = "vq0", "vq1", "shutdown"; + interrupt-parent = <&exti>; + interrupts = <68 1>; + status = "okay"; +}; + +&rng1 { + status = "okay"; +}; + +&rtc { + status = "okay"; +}; + +&sdmmc2 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc2_b4_pins_a &sdmmc2_d47_pins_d>; + pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_d>; + pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_d>; + non-removable; + no-sd; + no-sdio; + st,neg-edge; + bus-width = <8>; + vmmc-supply = <&v3v3>; + vqmmc-supply = <&v3v3>; + mmc-ddr-3_3v; + status = "okay"; +}; + diff --git a/arch/arm/boot/dts/stm32mp157c-odyssey.dts b/arch/arm/boot/dts/stm32mp157c-odyssey.dts new file mode 100644 index 000000000000..a7ffec8f1516 --- /dev/null +++ b/arch/arm/boot/dts/stm32mp157c-odyssey.dts @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * Copyright (C) 2020 Marcin Sloniewski . + */ + +/dts-v1/; + +#include "stm32mp157c-odyssey-som.dtsi" + +/ { + model = "Seeed Studio Odyssey-STM32MP157C Board"; + compatible = "seeed,stm32mp157c-odyssey", + "seeed,stm32mp157c-odyssey-som", "st,stm32mp157"; + + aliases { + ethernet0 = ðernet0; + serial0 = &uart4; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; +}; + +ðernet0 { + status = "okay"; + pinctrl-0 = <ðernet0_rgmii_pins_a>; + pinctrl-1 = <ðernet0_rgmii_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-mode = "rgmii-id"; + max-speed = <1000>; + phy-handle = <&phy0>; + assigned-clocks = <&rcc ETHCK_K>, <&rcc PLL4_P>; + assigned-clock-parents = <&rcc PLL4_P>; + assigned-clock-rates = <125000000>; /* Clock PLL4 to 750Mhz in ATF/U-Boot */ + st,eth-clk-sel; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@7 { /* KSZ9031RN */ + reg = <7>; + reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; /* ETH_RST# */ + reset-assert-us = <10000>; + reset-deassert-us = <300>; + }; + }; +}; + +&i2c1 { + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&i2c1_pins_a>; + pinctrl-1 = <&i2c1_sleep_pins_a>; + i2c-scl-rising-time-ns = <100>; + i2c-scl-falling-time-ns = <7>; + status = "okay"; + /delete-property/dmas; + /delete-property/dma-names; +}; + +&sdmmc1 { + pinctrl-names = "default", "opendrain", "sleep"; + pinctrl-0 = <&sdmmc1_b4_pins_a>; + pinctrl-1 = <&sdmmc1_b4_od_pins_a>; + pinctrl-2 = <&sdmmc1_b4_sleep_pins_a>; + cd-gpios = <&gpiob 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; + disable-wp; + st,neg-edge; + bus-width = <4>; + vmmc-supply = <&v3v3>; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&uart4_pins_a>; + status = "okay"; +}; + From 9e8f500af7c59d3057fb784d6c0c5b5cd1f9430f Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:27 +0200 Subject: [PATCH 09/20] ARM: dts: stm32: Add STM32MP1 UART8 RTS/CTS pinmux Add extra RTS/CTS line pinmux for STM32MP1 UART8. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Acked-by: Fabrice Gasnier Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15-pinctrl.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi index a47eaecbde42..d84686e00370 100644 --- a/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/stm32mp15-pinctrl.dtsi @@ -1718,6 +1718,14 @@ pins2 { }; }; + uart8_rtscts_pins_a: uart8rtscts-0 { + pins { + pinmux = , /* UART8_RTS */ + ; /* UART8_CTS */ + bias-disable; + }; + }; + spi4_pins_a: spi4-0 { pins { pinmux = , /* SPI4_SCK */ From 30e9af4ba3e11cd80f1b5063085f2b37aeecaf62 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:28 +0200 Subject: [PATCH 10/20] ARM: dts: stm32: Drop QSPI CS2 pinmux on DHCOM The QSPI CS2 is not used on DHCOM, remove the pinmux settings. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index d30a3c60da9b..60e3d6687f63 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -321,8 +321,8 @@ &pwr_regulators { &qspi { pinctrl-names = "default", "sleep"; - pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a &qspi_bk2_pins_a>; - pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a &qspi_bk2_sleep_pins_a>; + pinctrl-0 = <&qspi_clk_pins_a &qspi_bk1_pins_a>; + pinctrl-1 = <&qspi_clk_sleep_pins_a &qspi_bk1_sleep_pins_a>; reg = <0x58003000 0x1000>, <0x70000000 0x4000000>; #address-cells = <1>; #size-cells = <0>; From d0ce6f1be3d38de41369692449766dad86d21644 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Wed, 5 Aug 2020 14:36:29 +0200 Subject: [PATCH 11/20] ARM: dts: stm32: Enable RTS/CTS for DH PDK2 UART8 The DH PDK2 has RTS/CTS lines available on UART8, describe them in DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index 9e93f0a0d293..f8ac065d4597 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -271,7 +271,8 @@ &usart3 { &uart8 { pinctrl-names = "default"; - pinctrl-0 = <&uart8_pins_a>; + pinctrl-0 = <&uart8_pins_a &uart8_rtscts_pins_a>; + uart-has-rtscts; status = "okay"; }; From 9fc37291831fd85e579cacccb3d887c4f240f2e8 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Sat, 15 Aug 2020 00:50:07 +0200 Subject: [PATCH 12/20] ARM: dts: stm32: add display controller node to stm32h743 Declare LTDC (display controller) on stm32h743. Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 69e2f1e78ed6..2ac6e17c7035 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -329,6 +329,16 @@ usbotg_fs: usb@40080000 { status = "disabled"; }; + ltdc: display-controller@50001000 { + compatible = "st,stm32-ltdc"; + reg = <0x50001000 0x200>; + interrupts = <88>, <89>; + resets = <&rcc STM32H7_APB3_RESET(LTDC)>; + clocks = <&rcc LTDC_CK>; + clock-names = "lcd"; + status = "disabled"; + }; + mdma1: dma-controller@52000000 { compatible = "st,stm32h7-mdma"; reg = <0x52000000 0x1000>; From 33aa48808619393d70f103da85db03847f29b90f Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Sat, 15 Aug 2020 00:35:43 +0200 Subject: [PATCH 13/20] ARM: dts: stm32: add resets property to spi device nodes on stm32h743 The stm32 spi driver tries to determine the fifo size of spi devices dynamically. However, if the spi was already configured by the bootloader the fifo size check can become an endless loop, because the driver expects the spi to be in its initial "after device reset" state. The driver does already support resetting the spi device at probe, thus this patch adds only the required device tree properties Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 2ac6e17c7035..59995720c270 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -110,6 +110,7 @@ spi2: spi@40003800 { compatible = "st,stm32h7-spi"; reg = <0x40003800 0x400>; interrupts = <36>; + resets = <&rcc STM32H7_APB1L_RESET(SPI2)>; clocks = <&rcc SPI2_CK>; status = "disabled"; @@ -121,6 +122,7 @@ spi3: spi@40003c00 { compatible = "st,stm32h7-spi"; reg = <0x40003c00 0x400>; interrupts = <51>; + resets = <&rcc STM32H7_APB1L_RESET(SPI3)>; clocks = <&rcc SPI3_CK>; status = "disabled"; }; @@ -207,6 +209,7 @@ spi1: spi@40013000 { compatible = "st,stm32h7-spi"; reg = <0x40013000 0x400>; interrupts = <35>; + resets = <&rcc STM32H7_APB2_RESET(SPI1)>; clocks = <&rcc SPI1_CK>; status = "disabled"; }; @@ -217,6 +220,7 @@ spi4: spi@40013400 { compatible = "st,stm32h7-spi"; reg = <0x40013400 0x400>; interrupts = <84>; + resets = <&rcc STM32H7_APB2_RESET(SPI4)>; clocks = <&rcc SPI4_CK>; status = "disabled"; }; @@ -227,6 +231,7 @@ spi5: spi@40015000 { compatible = "st,stm32h7-spi"; reg = <0x40015000 0x400>; interrupts = <85>; + resets = <&rcc STM32H7_APB2_RESET(SPI5)>; clocks = <&rcc SPI5_CK>; status = "disabled"; }; @@ -382,6 +387,7 @@ spi6: spi@58001400 { compatible = "st,stm32h7-spi"; reg = <0x58001400 0x400>; interrupts = <86>; + resets = <&rcc STM32H7_APB4_RESET(SPI6)>; clocks = <&rcc SPI6_CK>; status = "disabled"; }; From 862f5c7ebc88e72990dd70c4d687b571ce999473 Mon Sep 17 00:00:00 2001 From: Tobias Schramm Date: Fri, 14 Aug 2020 20:11:25 +0200 Subject: [PATCH 14/20] ARM: dts: stm32: use stm32h7 usart compatible string for stm32h743 Previously the FIFO on the stm32h743 usart was not utilized, because the stm32f7 compatible configures it without FIFO support. Signed-off-by: Tobias Schramm Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32h743.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32h743.dtsi b/arch/arm/boot/dts/stm32h743.dtsi index 59995720c270..7febe19e780d 100644 --- a/arch/arm/boot/dts/stm32h743.dtsi +++ b/arch/arm/boot/dts/stm32h743.dtsi @@ -128,7 +128,7 @@ spi3: spi@40003c00 { }; usart2: serial@40004400 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40004400 0x400>; interrupts = <38>; status = "disabled"; @@ -196,7 +196,7 @@ dac2: dac@2 { }; usart1: serial@40011000 { - compatible = "st,stm32f7-uart"; + compatible = "st,stm32h7-uart"; reg = <0x40011000 0x400>; interrupts = <37>; status = "disabled"; From 9ad98319e95263469d8ca2cb543c37c5a2f40980 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Fri, 28 Aug 2020 14:14:12 +0200 Subject: [PATCH 15/20] ARM: dts: stm32: Swap PHY reset GPIO and TSC2004 IRQ on DHCOM SOM On the production revision of the SoM, 587-200, the PHY reset GPIO and touchscreen IRQs are swapped to prevent collision between EXTi IRQs, reflect that in DT. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi index 60e3d6687f63..b4b52cf634af 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-som.dtsi @@ -117,7 +117,7 @@ ðernet0 { max-speed = <100>; phy-handle = <&phy0>; st,eth-ref-clk-sel; - phy-reset-gpios = <&gpioh 15 GPIO_ACTIVE_LOW>; + phy-reset-gpios = <&gpioh 3 GPIO_ACTIVE_LOW>; mdio0 { #address-cells = <1>; @@ -285,7 +285,7 @@ touchscreen@49 { compatible = "ti,tsc2004"; reg = <0x49>; vio-supply = <&v3v3>; - interrupts-extended = <&gpioh 3 IRQ_TYPE_EDGE_FALLING>; + interrupts-extended = <&gpioh 15 IRQ_TYPE_EDGE_FALLING>; }; eeprom@50 { From 3c5c0eee95ece9a73969a94832093be8892cd4c1 Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:34:25 +0200 Subject: [PATCH 16/20] ARM: dts: stm32: Enable RTS/CTS for DH AV96 UART7 The DH AV96 has RTS/CTS lines available on UART7, describe them in DT. Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi index 905cd7bb98cf..ec02cee1dd9b 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcor-avenger96.dtsi @@ -351,6 +351,7 @@ &uart7 { label = "LS-UART0"; pinctrl-names = "default"; pinctrl-0 = <&uart7_pins_a>; + uart-has-rtscts; status = "okay"; }; From 57592d2a98dbc3bde3ddc062e91a8486bdcb211e Mon Sep 17 00:00:00 2001 From: Marek Vasut Date: Sat, 22 Aug 2020 22:32:55 +0200 Subject: [PATCH 17/20] ARM: dts: stm32: Fix DH PDK2 display PWM channel The display PWM channel is number 3 (PWM2 CH4), make it so. Fixes: 34e0c7847dcf ("ARM: dts: stm32: Add DH Electronics DHCOM STM32MP1 SoM and PDK2 board") Signed-off-by: Marek Vasut Cc: Alexandre Torgue Cc: Maxime Coquelin Cc: Patrice Chotard Cc: Patrick Delaunay Cc: linux-stm32@st-md-mailman.stormreply.com To: linux-arm-kernel@lists.infradead.org Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi index f8ac065d4597..5dff24e39af8 100644 --- a/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi +++ b/arch/arm/boot/dts/stm32mp15xx-dhcom-pdk2.dtsi @@ -25,7 +25,7 @@ clk_ext_audio_codec: clock-codec { display_bl: display-bl { compatible = "pwm-backlight"; - pwms = <&pwm2 0 500000 PWM_POLARITY_INVERTED>; + pwms = <&pwm2 3 500000 PWM_POLARITY_INVERTED>; brightness-levels = <0 16 22 30 40 55 75 102 138 188 255>; default-brightness-level = <8>; enable-gpios = <&gpioi 0 GPIO_ACTIVE_HIGH>; From bae2b7f6774b2db44f9001bee7465d4dadd1ede8 Mon Sep 17 00:00:00 2001 From: Ahmad Fatoum Date: Fri, 28 Aug 2020 15:00:02 +0200 Subject: [PATCH 18/20] ARM: dts: stm32: lxa-mc1: enable DDR50 mode on eMMC The "eMMC high-speed DDR mode (3.3V I/O)" at 50MHz is supported on the eMMC-interface of the lxa-mc1. Set it in the device tree to benefit from the speed improvement. Signed-off-by: Ahmad Fatoum Signed-off-by: Holger Assmann Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts index b85025d00943..1e5333fd437f 100644 --- a/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts +++ b/arch/arm/boot/dts/stm32mp157c-lxa-mc1.dts @@ -212,6 +212,7 @@ &sdmmc2 { pinctrl-1 = <&sdmmc2_b4_od_pins_a &sdmmc2_d47_pins_b>; pinctrl-2 = <&sdmmc2_b4_sleep_pins_a &sdmmc2_d47_sleep_pins_b>; bus-width = <8>; + mmc-ddr-3_3v; no-1-8-v; no-sd; no-sdio; From fdcf9ea31c33fe9c54dc0b99ca4f744813ba6840 Mon Sep 17 00:00:00 2001 From: Christophe Kerello Date: Fri, 4 Sep 2020 15:20:43 +0200 Subject: [PATCH 19/20] ARM: dts: stm32: add FMC2 EBI support for stm32mp157c This patch adds FMC2 External Bus Interface support on stm32mp157c. Signed-off-by: Christophe Kerello Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 43 ++++++++++++++++++--------- arch/arm/boot/dts/stm32mp157c-ev1.dts | 16 +++++----- 2 files changed, 38 insertions(+), 21 deletions(-) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index bfe29023fbd5..4fd757237b98 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -1302,23 +1302,38 @@ mdma1: dma-controller@58000000 { dma-requests = <48>; }; - fmc: nand-controller@58002000 { - compatible = "st,stm32mp15-fmc2"; - reg = <0x58002000 0x1000>, - <0x80000000 0x1000>, - <0x88010000 0x1000>, - <0x88020000 0x1000>, - <0x81000000 0x1000>, - <0x89010000 0x1000>, - <0x89020000 0x1000>; - interrupts = ; - dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>, - <&mdma1 20 0x10 0x12000a08 0x0 0x0>, - <&mdma1 21 0x10 0x12000a0a 0x0 0x0>; - dma-names = "tx", "rx", "ecc"; + fmc: memory-controller@58002000 { + #address-cells = <2>; + #size-cells = <1>; + compatible = "st,stm32mp1-fmc2-ebi"; + reg = <0x58002000 0x1000>; clocks = <&rcc FMC_K>; resets = <&rcc FMC_R>; status = "disabled"; + + ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */ + <1 0 0x64000000 0x04000000>, /* EBI CS 2 */ + <2 0 0x68000000 0x04000000>, /* EBI CS 3 */ + <3 0 0x6c000000 0x04000000>, /* EBI CS 4 */ + <4 0 0x80000000 0x10000000>; /* NAND */ + + nand-controller@4,0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "st,stm32mp1-fmc2-nfc"; + reg = <4 0x00000000 0x1000>, + <4 0x08010000 0x1000>, + <4 0x08020000 0x1000>, + <4 0x01000000 0x1000>, + <4 0x09010000 0x1000>, + <4 0x09020000 0x1000>; + interrupts = ; + dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>, + <&mdma1 20 0x2 0x12000a08 0x0 0x0>, + <&mdma1 21 0x2 0x12000a0a 0x0 0x0>; + dma-names = "tx", "rx", "ecc"; + status = "disabled"; + }; }; qspi: spi@58003000 { diff --git a/arch/arm/boot/dts/stm32mp157c-ev1.dts b/arch/arm/boot/dts/stm32mp157c-ev1.dts index 85628e16d2d5..a55e80ce2602 100644 --- a/arch/arm/boot/dts/stm32mp157c-ev1.dts +++ b/arch/arm/boot/dts/stm32mp157c-ev1.dts @@ -158,14 +158,16 @@ &fmc { pinctrl-0 = <&fmc_pins_a>; pinctrl-1 = <&fmc_sleep_pins_a>; status = "okay"; - #address-cells = <1>; - #size-cells = <0>; - nand@0 { - reg = <0>; - nand-on-flash-bbt; - #address-cells = <1>; - #size-cells = <1>; + nand-controller@4,0 { + status = "okay"; + + nand@0 { + reg = <0>; + nand-on-flash-bbt; + #address-cells = <1>; + #size-cells = <1>; + }; }; }; From 71593c519f162b5f54bafed085cdddc7a883894d Mon Sep 17 00:00:00 2001 From: Alexandre Torgue Date: Thu, 17 Sep 2020 05:00:35 +0200 Subject: [PATCH 20/20] ARM: dts: stm32: add arm-pmu node on stm32mp15 Add arm-pmu node on stm32mp15. Signed-off-by: Alexandre Torgue Signed-off-by: Marek Vasut # update to linux-next Tested-by: Marek Vasut # on DH PDK2 and Avenger96 Signed-off-by: Alexandre Torgue --- arch/arm/boot/dts/stm32mp151.dtsi | 7 +++++++ arch/arm/boot/dts/stm32mp153.dtsi | 6 ++++++ 2 files changed, 13 insertions(+) diff --git a/arch/arm/boot/dts/stm32mp151.dtsi b/arch/arm/boot/dts/stm32mp151.dtsi index 4fd757237b98..84757901cd8d 100644 --- a/arch/arm/boot/dts/stm32mp151.dtsi +++ b/arch/arm/boot/dts/stm32mp151.dtsi @@ -23,6 +23,13 @@ cpu0: cpu@0 { }; }; + arm-pmu { + compatible = "arm,cortex-a7-pmu"; + interrupts = ; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; diff --git a/arch/arm/boot/dts/stm32mp153.dtsi b/arch/arm/boot/dts/stm32mp153.dtsi index 6d9ab08667fc..1c1889b194cf 100644 --- a/arch/arm/boot/dts/stm32mp153.dtsi +++ b/arch/arm/boot/dts/stm32mp153.dtsi @@ -16,6 +16,12 @@ cpu1: cpu@1 { }; }; + arm-pmu { + interrupts = , + ; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; + soc { m_can1: can@4400e000 { compatible = "bosch,m_can";