dt-bindings: mtd: cdns,hp-nfc: Add dma-coherent property

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The Cadence HP NAND Flash Controller on supports DMA transactions through
a coherent interconnect. In previous generations SoC (Stratix10 and Agilex)
the interconnect was non-coherent, hence there is no need for dma-coherent
property to be presence. In Agilex 5, the architecture has changed. It
introduced a coherent interconnect that supports cache-coherent DMA.

Signed-off-by: Khairul Anuar Romli <khairul.anuar.romli@altera.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>

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Khairul Anuar Romli 2026-01-31 11:26:11 -06:00 • committed by Miquel Raynal

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commit 8753827592

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Documentation/devicetree/bindings/mtd/cdns,hp-nfc.yaml

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