drm/msm/dpu: add setup_clk_force_ctrl() op to sspp & wb

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Starting from SM8550, the SSPP & WB clock controls are moved
the SSPP and WB register range, as it's called "VBIF_CLK_SPLIT"
downstream.

Implement setup_clk_force_ctrl() only starting from major version 9
which corresponds to SM8550 MDSS.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Patchwork: https://patchwork.freedesktop.org/patch/562322/
Signed-off-by: Rob Clark <robdclark@chromium.org>

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This commit is contained in:

Neil Armstrong 2023-10-12 11:01:28 +02:00 • committed by Rob Clark

parent 76191dc11e

commit 87e9686727

5 changed files with 54 additions and 10 deletions

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21

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c

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12

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h

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20

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.c

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7

drivers/gpu/drm/msm/disp/dpu1/dpu_hw_wb.h

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4

drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c

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