PCI: tegra194: Use aspm-l1-entry-delay-ns DT property for L1 entrance latency

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Program the Synopsys DesignWare PORT_AFR L1 entrance latency field from the
optional aspm-l1-entry-delay-ns device tree property (nanoseconds).

Convert delay to whole microseconds with ceiling division (DIV_ROUND_UP),
then derive the 3-bit hw encoding as the minimum of order_base_2(us) and 7.
If the property is not present or cannot be read, default to 7.

Hardware encoding (PORT_AFR L1 entrance latency, bits 27:29):

  +--------------------------+----------+
  | Advertised maximum       | Code     |
  +--------------------------+----------+
  | Maximum of 1 us          | 000b     |
  +--------------------------+----------+
  | Maximum of 2 us          | 001b     |
  +--------------------------+----------+
  | Maximum of 4 us          | 010b     |
  +--------------------------+----------+
  | Maximum of 8 us          | 011b     |
  +--------------------------+----------+
  | Maximum of 16 us         | 100b     |
  +--------------------------+----------+
  | Maximum of 32 us         | 101b     |
  +--------------------------+----------+
  | Maximum of 64 us         | 110b     |
  +--------------------------+----------+
  | Rest                     | 111b     |
  +--------------------------+----------+

Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://patch.msgid.link/20260515070753.3852840-2-mmaddireddy@nvidia.com

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Manikanta Maddireddy 2026-05-15 12:37:52 +05:30 • committed by Manivannan Sadhasivam

parent 254f49634e

commit 87f493041e

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drivers/pci/controller/dwc/pcie-tegra194.c

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