arm64: cpu_errata: Remove ARM64_MISMATCHED_CACHE_LINE_SIZE

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There's no need to treat mismatched cache-line sizes reported by CTR_EL0
differently to any other mismatched fields that we treat as "STRICT" in
the cpufeature code. In both cases we need to trap and emulate EL0
accesses to the register, so drop ARM64_MISMATCHED_CACHE_LINE_SIZE and
rely on ARM64_MISMATCHED_CACHE_TYPE instead.

Reviewed-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: move ARM64_HAS_CNP in the empty cpucaps.h slot]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>

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Will Deacon 2018-09-19 11:41:21 +01:00 • committed by Catalin Marinas

parent ab510027dc

commit 880f7cc472

3 changed files with 7 additions and 20 deletions

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7

arch/arm64/include/asm/assembler.h

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5

arch/arm64/include/asm/cpucaps.h

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15

arch/arm64/kernel/cpu_errata.c

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