From 8961ea13bec45eedbd44788df597d979023405fd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Wed, 26 Aug 2026 16:40:26 +0300 Subject: [PATCH] drm/i915/cdclk: s/intel_/dg2_/ for DG2 specific stuff MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit intel_pcode_*notify() are all DG2 specific code. Rename them to have a dg2_ namespace. Reviewed-by: Jani Nikula Signed-off-by: Ville Syrjälä Link: https://patch.msgid.link/20260826134033.13976-8-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/intel_cdclk.c | 31 ++++++++++------------ 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c index 4ebda4e289d0..a8112d9f4b9e 100644 --- a/drivers/gpu/drm/i915/display/intel_cdclk.c +++ b/drivers/gpu/drm/i915/display/intel_cdclk.c @@ -2624,19 +2624,16 @@ void intel_cdclk_dump_config(struct intel_display *display, cdclk_config->voltage_level); } -static void intel_pcode_notify(struct intel_display *display, - u8 voltage_level, - u8 active_pipe_count, - u16 cdclk, - bool cdclk_update_valid, - bool pipe_count_update_valid) +static void dg2_cdclk_pcode_notify(struct intel_display *display, + u8 voltage_level, + u8 active_pipe_count, + u16 cdclk, + bool cdclk_update_valid, + bool pipe_count_update_valid) { int ret; u32 update_mask = 0; - if (!display->platform.dg2) - return; - update_mask = DISPLAY_TO_PCODE_UPDATE_MASK(cdclk, active_pipe_count, voltage_level); if (cdclk_update_valid) @@ -2721,7 +2718,7 @@ static int dg2_power_well_count(struct intel_display *display, return display->platform.dg2 ? hweight8(cdclk_state->active_pipes) : 0; } -static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) +static void dg2_cdclk_pcode_pre_notify(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); const struct intel_cdclk_state *old_cdclk_state = @@ -2767,11 +2764,11 @@ static void intel_cdclk_pcode_pre_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = dg2_power_well_count(display, new_cdclk_state); - intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, - change_cdclk, update_pipe_count); + dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, + change_cdclk, update_pipe_count); } -static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) +static void dg2_cdclk_pcode_post_notify(struct intel_atomic_state *state) { struct intel_display *display = to_intel_display(state); const struct intel_cdclk_state *new_cdclk_state = @@ -2808,8 +2805,8 @@ static void intel_cdclk_pcode_post_notify(struct intel_atomic_state *state) if (update_pipe_count) num_active_pipes = dg2_power_well_count(display, new_cdclk_state); - intel_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, - update_cdclk, update_pipe_count); + dg2_cdclk_pcode_notify(display, voltage_level, num_active_pipes, cdclk_mhz, + update_cdclk, update_pipe_count); } bool intel_cdclk_is_decreasing_later(struct intel_atomic_state *state) @@ -2875,7 +2872,7 @@ intel_set_cdclk_pre_plane_update(struct intel_atomic_state *state) drm_WARN_ON(display->drm, !new_cdclk_state->base.changed); if (display->platform.dg2) - intel_cdclk_pcode_pre_notify(state); + dg2_cdclk_pcode_pre_notify(state); intel_set_cdclk(display, &cdclk_config, pipe, "Pre changing CDCLK to"); @@ -2919,7 +2916,7 @@ intel_set_cdclk_post_plane_update(struct intel_atomic_state *state) "Post changing CDCLK to"); if (display->platform.dg2) - intel_cdclk_pcode_post_notify(state); + dg2_cdclk_pcode_post_notify(state); } /* pixels per CDCLK */