clk: mediatek: fix PWM clock source by adding a fixed-factor clock

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The clock for which all PWM devices on MT7623 or MT2701 actually depending
on has to be divided by four from its parent clock axi_sel in the clock
path prior to PWM devices.

Consequently, adding a fixed-factor clock axisel_d4 as one-fourth of
clock axi_sel allows that PWM devices can have the correct resolution
calculation.

Cc: stable@vger.kernel.org
Fixes: e986211827 ("clk: mediatek: Add MT2701 clock support")
Signed-off-by: Sean Wang <sean.wang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>

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Sean Wang 2018-03-01 11:27:51 +08:00 • committed by Stephen Boyd

parent 55a5fcafe3

commit 89cd7aec21

1 changed files with 8 additions and 7 deletions

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drivers/clk/mediatek/clk-mt2701.c

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