x86/intel_rdt: More precise L2 hit/miss measurements

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Intel Goldmont processors supports non-architectural precise events that
can be used to give us more insight into the success of L2 cache
pseudo-locking on these platforms.

Introduce a new measurement trigger that will enable two precise events,
MEM_LOAD_UOPS_RETIRED.L2_HIT and MEM_LOAD_UOPS_RETIRED.L2_MISS, while
accessing pseudo-locked data. A new tracepoint, pseudo_lock_l2, is
created to make these results visible to the user.

Signed-off-by: Reinette Chatre <reinette.chatre@intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: fenghua.yu@intel.com
Cc: tony.luck@intel.com
Cc: vikas.shivappa@linux.intel.com
Cc: gavin.hindman@intel.com
Cc: jithu.joseph@intel.com
Cc: dave.hansen@intel.com
Cc: hpa@zytor.com
Link: https://lkml.kernel.org/r/06b1456da65b543479dac8d9493e41f92f175d6c.1529706536.git.reinette.chatre@intel.com

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Reinette Chatre 2018-06-22 15:42:28 -07:00 • committed by Thomas Gleixner

parent 746e08590b

commit 8a2fc0e1bc

2 changed files with 146 additions and 9 deletions

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145

arch/x86/kernel/cpu/intel_rdt_pseudo_lock.c

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10

arch/x86/kernel/cpu/intel_rdt_pseudo_lock_event.h

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