drm/i915/xe2lpd: implement WA for underruns while enabling FBC

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FIFO underruns are observed when FBC is enabled on plane 2 or
plane 3. Recommended WA is to update the FBC enabling sequence.
The plane binding register bits need to be updated separately
before programming the FBC enable bit.

Bspec: 74151
Reviewed-by: Mika Kahola <mika.kahola@intel.com> #v3
Signed-off-by: Vinod Govindapillai <vinod.govindapillai@intel.com>
Reviewed-by: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20231111114320.87277-2-vinod.govindapillai@intel.com

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Vinod Govindapillai 2023-11-11 13:43:20 +02:00 • committed by Mika Kahola

parent dd99d5b1ab

commit 8a4353d077

1 changed files with 7 additions and 1 deletions

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drivers/gpu/drm/i915/display/intel_fbc.c

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