staging: fsl-dpaa2/eth: Change RX buffer alignment

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The WRIOP hardware block v1.0.0 (found on LS2080A board)
requires data in RX buffers to be aligned to 256B, but
newer revisions (e.g. on LS2088A, LS1088A) only require
64B alignment.

Check WRIOP version and decide at runtime which alignment
requirement to configure for ingress buffers.

Signed-off-by: Bogdan Purcareata <bogdan.purcareata@nxp.com>
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>

...

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Bogdan Purcareata 2017-10-29 08:20:42 +00:00 • committed by Greg Kroah-Hartman

parent 3c2192863f

commit 8a4fd8778b

2 changed files with 33 additions and 12 deletions

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18

drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.c

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27

drivers/staging/fsl-dpaa2/ethernet/dpaa2-eth.h

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