i2c: cadence: Check for errata condition involving master receive

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Cadence I2C controller has the following bugs:
- completion indication is not given to the driver at the end of
a read/receive transfer with HOLD bit set.
- Invalid read transaction are generated on the bus when HW timeout
condition occurs with HOLD bit set.

As a result of the above, if a set of messages to be transferred with
repeated start includes any message following a read message,
completion is never indicated and timeout occurs.
Hence a check is implemented to return -EOPNOTSUPP for such sequences.

Signed-off-by: Harini Katakam <harinik@xilinx.com>
Signed-off-by: Vishnu Motghare <vishnum@xilinx.com>
[wsa: fixed some whitespaces]
Signed-off-by: Wolfram Sang <wsa@the-dreams.de>

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Harini Katakam 2015-01-14 00:04:59 +05:30 • committed by Wolfram Sang

parent ef2829144d

commit 8a86c3aee0

1 changed files with 14 additions and 0 deletions

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drivers/i2c/busses/i2c-cadence.c

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