drm/i915/dip: Store SDP transmission lines in crtc_state

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Currently the driver only programs the transmission line for the
Adaptive-Sync SDP, while the hardware controls the transmission lines for
other SDPs.

Starting with Xe3p_lpd, the hardware allows the driver to program
transmission lines for additional DP SDPs. Prepare for this by adding
fields to struct intel_crtc_state to store SDP transmission lines, and
include them in pipe config comparison.

The SDP transmission line fields track vrr.vsync_start/vtotal, which are
allowed to change during a seamless LRR fastset. Guard their pipe config
comparison under !fastset, same as vrr.vsync_start/vsync_end, so a fastset
is not unnecessarily turned into a full modeset.

Signed-off-by: Ankit Nautiyal <ankit.k.nautiyal@intel.com>
Reviewed-by: Suraj Kandpal <suraj.kandpal@intel.com>
Link: https://patch.msgid.link/20260915164657.3429075-10-ankit.k.nautiyal@intel.com

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This commit is contained in:

Ankit Nautiyal 2026-09-15 22:16:50 +05:30

parent 45b6a7f1b8

commit 8aeed61a7d

2 changed files with 11 additions and 0 deletions

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5

drivers/gpu/drm/i915/display/intel_display.c

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6

drivers/gpu/drm/i915/display/intel_display_types.h

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