mmc: msm_sdcc: Wrap readl/writel calls with appropriate clk delays

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As it turns out, all sdcc register writes must be delayed by at
least 3 core clock cycles for the writes to take effect. *sigh*

    Also removes the 30us constant delay on clock enable in favor
of a 3 core clock delay.

Signed-off-by: San Mehat <san@google.com>
Signed-off-by: Daniel Walker <dwalker@codeaurora.org>

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San Mehat 2009-11-16 10:17:30 -08:00 • committed by Daniel Walker

parent 865c8064a2

commit 8b1c2ba274

1 changed files with 61 additions and 55 deletions

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116

drivers/mmc/host/msm_sdcc.c

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