clk: samsung: add BPLL rate table for Exynos 5422 SoC

Browse source

Add new table rate for BPLL for Exynos5422 SoC supporting Dynamic Memory
Controller frequencies for driver's DRAM timings.

Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>

...

This commit is contained in:

Lukasz Luba 2019-06-05 18:54:00 +02:00 • committed by Sylwester Nawrocki

parent cc9bdecf4b

commit 8b4a7acf7b

1 changed files with 16 additions and 1 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

17

drivers/clk/samsung/clk-exynos5420.c

View file