riscv: implement remote sfence.i using IPIs

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The RISC-V ISA only supports flushing the instruction cache for the
local CPU core.  Currently we always offload the remote TLB flushing to
the SBI, which then issues an IPI under the hoods.  But with M-mode
we do not have an SBI so we have to do it ourselves.   IPI to the
other nodes using the existing kernel helpers instead if we have
native clint support and thus can IPI directly from the kernel.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Reviewed-by: Anup Patel <anup@brainfault.org>
[paul.walmsley@sifive.com: cleaned up code comment]
Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>

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Christoph Hellwig 2019-10-28 13:10:36 +01:00 • committed by Paul Walmsley

parent 3320648ecc

commit 8bf90f320d

2 changed files with 21 additions and 6 deletions

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3

arch/riscv/include/asm/sbi.h

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24

arch/riscv/mm/cacheflush.c

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