drm/amdgpu: enable only one high prio compute queue

Browse source

For high priority compute to work properly we need to enable
wave limiting on gfx pipe. Wave limiting is done through writing
into mmSPI_WCL_PIPE_PERCENT_GFX register. Enable only one high
priority compute queue to avoid race condition between multiple
high priority compute queues writing that register simultaneously.

Signed-off-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

...

This commit is contained in:

Nirmoy Das 2021-02-01 12:12:34 +01:00 • committed by Alex Deucher

parent ebdd2e9d1a

commit 8c0225d792

5 changed files with 15 additions and 21 deletions

Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL

Download patch file Download diff file Expand all files Collapse all files

15

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.c

View file

2

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

View file

6

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

View file

6

drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c

View file

7

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

View file