x86, cacheinfo: Carve out L3 cache slot accessors

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This is in preparation for disabling L3 cache indices after having
received correctable ECCs in the L3 cache. Now we allow for initial
setting of a disabled index slot (write once) and deny writing new
indices to it after it has been disabled. Also, we deny using both slots
to disable one and the same index.

Userspace can restore the previously disabled indices by rewriting those
sysfs entries when booting.

Cleanup and reorganize code while at it.

Signed-off-by: Borislav Petkov <borislav.petkov@amd.com>
LKML-Reference: <20100602161840.GI18327@aftab>
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>

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Borislav Petkov 2010-06-02 18:18:40 +02:00 • committed by H. Peter Anvin

parent d6d4d4205c

commit 8cc1176e5d

1 changed files with 82 additions and 26 deletions

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arch/x86/kernel/cpu/intel_cacheinfo.c

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