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can: flexcan: convert struct flexcan_priv::rx_mask{1,2} to rx_mask
The flexcan IP core has up to 64 mailboxes, each one has a corresponding interrupt bit in the iflag1 or iflag2 registers and a mask bit in the imask1 or imask2 registers. In the timestamp (i.e. non FIFO) mode the driver needs to mask out all non RX interrupt sources and uses the precomputed values rx_mask1 and rx_mask2 of struct flexcan_priv for this. This patch merges the two u32 rx_mask1 and rx_mask2 to a single u64 rx_mask variable, which simplifies the code a bit. Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
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