drm/i915/gvt: factor out tlb and mocs register offset table

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Factor out tlb and mocs register offset table to fix the issues reported
by klocwork, #512 and #550. Mostly, the reason why the klocwork reports
these problems is because there can be possbilities for platforms, which
have more rings than the ring offset table, to take the dirty data from
the stack as the register offset. It results to a random HW register
offset writting in this scenairo when doing context switch between vGPUs.

After the factoring, the ring offset table of TLB and MOCS should be per
platform.

v2:

- Enable TLB register switch for GEN8. (Zhenyu)

Reviewed-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Zhi Wang <zhi.a.wang@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>

...

This commit is contained in:

Zhi Wang 2019-07-22 14:07:07 +03:00 • committed by Zhenyu Wang

parent f8871ec8fc

commit 8cfbca7848

2 changed files with 43 additions and 18 deletions

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4

drivers/gpu/drm/i915/gvt/gvt.h

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57

drivers/gpu/drm/i915/gvt/mmio_context.c

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