drm/i915: Use PIPE_CONTROL for flushing on gen6+.

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v2 by danvet: Use a new flag to flush the render target cache on gen6+
(hw reuses the old write flush bit), as suggested by Ben Widawsdy.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
[danvet: this seems to fix cairo-perf-trace hangs on my snb]
Signed-Off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>

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Jesse Barnes 2011-10-16 10:23:31 +02:00 • committed by Keith Packard

parent 9d971b3753

commit 8d31528703

2 changed files with 130 additions and 12 deletions

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6

drivers/gpu/drm/i915/i915_reg.h

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136

drivers/gpu/drm/i915/intel_ringbuffer.c

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